From 6ebebae7700b0e52e2dfd1eec74cf557a97247b3 Mon Sep 17 00:00:00 2001
From: modeco80 <lily.modeco80@protonmail.ch>
Date: Tue, 18 Jul 2023 00:47:10 -0400
Subject: [PATCH] Use an output iterator for the lucore stdout sink

---
 native/projects/lucore/src/Logger.cpp       | 31 ++++++++++++++---
 native/projects/riscv/include/riscv/Bus.hpp | 10 ++----
 native/projects/riscv/include/riscv/CPU.hpp | 38 +++++++++++++++++++--
 native/projects/riscv/src/Bus.cpp           |  5 +++
 4 files changed, 70 insertions(+), 14 deletions(-)

diff --git a/native/projects/lucore/src/Logger.cpp b/native/projects/lucore/src/Logger.cpp
index d075697..86d2637 100644
--- a/native/projects/lucore/src/Logger.cpp
+++ b/native/projects/lucore/src/Logger.cpp
@@ -1,3 +1,6 @@
+#include <bits/iterator_concepts.h>
+
+#include <cstddef>
 #include <iostream>
 #include <lucore/Logger.hpp>
 
@@ -35,11 +38,31 @@ namespace lucore {
 	}
 
 	void StdoutSink::OutputMessage(const Logger::MessageData& data) {
-		// This is very nasty, but required until more standard libraries support the C++23 <print>
+		// This is kinda iffy, but required until more standard libraries support the C++23 <print>
 		// header.
-		std::puts(std::format("[Lucore/{}] [{}] {}", Logger::SeverityToString(data.severity),
-							  data.time, std::vformat(data.format, data.args))
-				  .c_str());
+		struct FileOutIterator {
+			using iterator_category = std::output_iterator_tag;
+			using value_type = void;
+			using difference_type = std::ptrdiff_t;
+			using pointer = void;
+			using reference = void;
+
+			FileOutIterator(std::FILE* file) : file(file) {}
+			FileOutIterator& operator*() { return *this; }
+			FileOutIterator& operator++() { return *this; }
+			FileOutIterator& operator++(int) { return *this; }
+
+			FileOutIterator& operator=(const char& val) {
+				fputc(val, file);
+				return *this;
+			}
+
+		   private:
+			std::FILE* file;
+		};
+		std::format_to(FileOutIterator(data.severity < Logger::MessageSeverity::Error ? stdout : stderr), "[Lucore/{}] [{}] {}\n",
+					   Logger::SeverityToString(data.severity), data.time,
+					   std::vformat(data.format, data.args));
 	}
 
 	void LoggerAttachStdout() {
diff --git a/native/projects/riscv/include/riscv/Bus.hpp b/native/projects/riscv/include/riscv/Bus.hpp
index d9a9cb5..43ba5b8 100644
--- a/native/projects/riscv/include/riscv/Bus.hpp
+++ b/native/projects/riscv/include/riscv/Bus.hpp
@@ -29,12 +29,8 @@ namespace riscv {
 			/// the ability to... well, clock!
 			virtual void Clock() {}
 
-			// TODO(feat): Need to implement ability to generate interrupts
-			// from devices. This needs to be implemented to facilitate the
-			// implementation of the timer device as an actual Device implmentation
-			// instead of poorly hard-coding it into the CPU core logic.
-			//
-			// Also, default implementations of Peek* and Poke* should trap.
+			// TODO(feat): default implementations of Peek* and Poke* should exist
+			// and trap the CPU (similarly to what happens if a unmapped bus read occurs).
 
 
 			// Peek() -> reads a value from this device.
@@ -49,6 +45,7 @@ namespace riscv {
 
 		};
 
+		Bus(CPU* cpu);
 		~Bus();
 
 		/// Attach a device to the bus.
@@ -66,7 +63,6 @@ namespace riscv {
 		/// Clock all clocked devices.
 		void Clock();
 
-		// 
 		u8 PeekByte(AddressT address);
 		u16 PeekShort(AddressT address);
 		u32 PeekWord(AddressT address);
diff --git a/native/projects/riscv/include/riscv/CPU.hpp b/native/projects/riscv/include/riscv/CPU.hpp
index 87dbba9..bc8c88c 100644
--- a/native/projects/riscv/include/riscv/CPU.hpp
+++ b/native/projects/riscv/include/riscv/CPU.hpp
@@ -1,11 +1,43 @@
-
+#include <riscv/Bus.hpp>
+#include <riscv/Types.hpp>
 
 namespace riscv {
 
-	/** The CPU core. There will be one of these in a [System]. */
+	/** The CPU core. */
 	struct CPU {
+		struct State {
+			u32 gpr[32];
+			u32 pc;
+			u32 mstatus;
+			u32 cyclel;
+			u32 cycleh;
 
+			u32 timerl;
+			u32 timerh;
+			u32 timermatchl;
+			u32 timermatchh;
 
+			u32 mscratch;
+			u32 mtvec;
+			u32 mie;
+			u32 mip;
+
+			u32 mepc;
+			u32 mtval;
+			u32 mcause;
+
+			// Note: only a few bits are used.  (Machine = 3, User = 0)
+			// Bits 0..1 = privilege.
+			// Bit 2 = WFI (Wait for interrupt)
+			// Bit 3+ = Load/Store reservation LSBs.
+			u32 extraflags;
+		};
+
+		State& GetState() { return state; }
+
+	   private:
+		State state;
+		Bus bus;
 	};
 
-}
+} // namespace riscv
diff --git a/native/projects/riscv/src/Bus.cpp b/native/projects/riscv/src/Bus.cpp
index 121276b..9626652 100644
--- a/native/projects/riscv/src/Bus.cpp
+++ b/native/projects/riscv/src/Bus.cpp
@@ -3,6 +3,11 @@
 
 namespace riscv {
 
+	Bus::Bus(CPU* cpu)
+		: attachedCpu(cpu) {
+
+	}
+
 	Bus::~Bus() {
 		// Free all devices
 		for(auto& pair : mapped_devices)