gmod-lcpu/native/projects/riscv
Lily Tsuru 0d6646f8cb switch to Tier0 LoggingSystem_* 2023-07-18 17:38:33 -04:00
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include/riscv switch to Tier0 LoggingSystem_* 2023-07-18 17:38:33 -04:00
src RamDevice is public 2023-07-18 02:05:39 -04:00
CMakeLists.txt RamDevice is public 2023-07-18 02:05:39 -04:00
README.md move all native projects to native/projects 2023-07-16 05:46:49 -04:00

README.md

riscv

This is the RISC-V emulation core that LCPU uses in its native emulation module.

This is based off cnlohr/mini-rv32ima, but:

  • Rewritten in C++20 (because I like sanity)
  • Cleaned up somewhat
  • Moved ALL device and MMIO code to seperate interfaces
    • Re-implemented the timer device and the UART as said oop interface
      • Lua devices use a wrapper which can contain lua callbacks