History

Lily Tsuru 8eaf05a8ac riscv: Heavy bus refactor. It now doesn't assume literally every device would map something to memory. This should also fix some API orthogonality issues (ergo the CPU being treated specially)		2023-07-21 06:32:04 -04:00
..
include/riscv	riscv: Heavy bus refactor.	2023-07-21 06:32:04 -04:00
src	riscv: Heavy bus refactor.	2023-07-21 06:32:04 -04:00
CMakeLists.txt	riscv: Heavy bus refactor.	2023-07-21 06:32:04 -04:00
README.md	move all native projects to native/projects	2023-07-16 05:46:49 -04:00

README.md

riscv

This is the RISC-V emulation core that LCPU uses in its native emulation module.

This is based off cnlohr/mini-rv32ima, but:

Rewritten in C++20 (because I like sanity)
Cleaned up somewhat
Moved ALL device and MMIO code to seperate interfaces
- Re-implemented the timer device and the UART as said oop interface
  - Lua devices use a wrapper which can contain lua callbacks