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Lily Tsuru aa66a1ff2e riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00
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include/riscv riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00
src riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00
CMakeLists.txt riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00
README.md riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00

README.md

riscv

This is a simple RISC-V RV32IMA emulation library.

This is based off cnlohr/mini-rv32ima, but:

  • Rewritten in C++20 (because I like sanity)
  • Cleaned up vastly
  • Moved ALL device and MMIO code to seperate interfaces

Depends on lucore.