Lily Tsuru
9d7ef71d3b
start skeleton gmod module |
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| README.md | ||
README.md
riscv
This is the RISC-V emulation core that LCPU uses in its native emulation module.
This is based off cnlohr/mini-rv32ima, but:
- Rewritten in C++20 (because I like sanity)
- Cleaned up somewhat
- Moved ALL device and MMIO code to seperate interfaces
- Re-implemented the timer device and the UART as said oop interface
- Lua devices use a wrapper which can contain lua callbacks
- Re-implemented the timer device and the UART as said oop interface