37 lines
791 B
Makefile
37 lines
791 B
Makefile
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# Common GNU Make rules for building the project
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# This makefile is expected to be included after the variables given
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# have been defined:
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#
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# NAME=name
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#
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# TARGET=ee|iop
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#
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# KIND=bin|lib
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#
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# SRCS=[... source-file-list]
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#
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debug_Valid := y
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release_Valid := y
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ifneq ($($(CONFIG)_Valid),y)
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$(error Invalid configuration $(CONFIG) specified)
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endif
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BINDIR = $(TOP)/bin
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OBJDIR = obj/$(CONFIG)
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# include target-specific recipies specifying how to
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# build for the target.
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include $(TOP)/build/$(TARGET)-common.mk
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#include $(TOP)/build/$(TARGET)-$(KIND).mk
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FINALNAME=$(NAME)_$(CONFIG)
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OBJECTS := $(patsubst %.c,obj/$(CONFIG)/%.o,$(filter %.c,$(SRCS)))
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OBJECTS += $(patsubst %.cpp,obj/$(CONFIG)/%.o,$(filter %.cpp,$(SRCS)))
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OBJECTS += $(patsubst %.s,obj/$(CONFIG)/%.o,$(filter %.s,$(SRCS)))
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