# Common GNU Make rules for building targets (reducing boilerplate)

# This makefile is expected to be included after the variables given
# *have* been defined:
#
# NAME=name
#
# TARGET=ee|iop
#
# KIND=bin|lib
#
# SRCS=[... source-file-list]
#

debug_Valid := y
release_Valid := y

ifneq ($($(CONFIG)_Valid),y)
$(error Invalid configuration $(CONFIG) specified)
endif

BINDIR = $(TOP)/bin
OBJDIR = obj/$(CONFIG)


FINALNAME=$(NAME)_$(CONFIG)

OBJECTS := $(patsubst %.c,obj/$(CONFIG)/%.o,$(filter %.c,$(SRCS)))
OBJECTS += $(patsubst %.cpp,obj/$(CONFIG)/%.o,$(filter %.cpp,$(SRCS)))
OBJECTS += $(patsubst %.s,obj/$(CONFIG)/%.o,$(filter %.s,$(SRCS)))

CFLAGS := $(CFLAGS) $(INCS)

# include target-specific recipies specifying how to 
# build for the target.
include $(TOP)/build/targets/$(TARGET).mk