920 lines
32 KiB
Plaintext
920 lines
32 KiB
Plaintext
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//////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// Notes:
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//
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// Simple Driver for Intel 8254x PCI Ethernet Cards.
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//
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// Useful reference URLs:
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// http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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//
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// We use standard IP/TCP checksum offloading.
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//
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// The driver currently runs in interrupt driven mode using hardware based
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// interrupt throttling.
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//
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// Phy handling is automatic and relies on attached phy supporting
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// auto-negotiation. The phy update interrupt is used to keep track
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// of phy state.
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//
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// TODO:
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//
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// - Flow Control Support
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// - Support for packet fragments (all packets must have a single fragment
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// currently)
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// - Jumbo Packets
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// - Transmit TCP/IP checksum offloading
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//
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//#define DEBUG_INTEL
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using System;
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using System.Threading;
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using System.Diagnostics;
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using System.Collections;
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using Microsoft.Contracts;
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using Microsoft.Singularity.Channels;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Configuration;
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using Microsoft.Singularity.Io.Net;
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using Microsoft.Singularity.V1.Services;
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using Microsoft.Singularity.Drivers;
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using Microsoft.SingSharp;
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using Microsoft.Singularity.Directory;
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using Microsoft.Singularity.Extending;
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using Drivers.Net;
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namespace Microsoft.Singularity.Drivers.Network.Intel
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{
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[CLSCompliant(false)]
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public class Intel
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{
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internal const uint MaxTxFragmentsPerPacket = 1; // Todo: allow frags
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internal const uint MaxRxFragmentsPerPacket = 1; // Todo: allow frags
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internal const uint MaxRxPackets = 1023; // one less than full buffer
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internal const uint MaxTxPackets = 2047;
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// Fragments must be power of two.
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internal const uint MaxTxFragmentsInRing = ((MaxTxPackets + 1) *
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MaxTxFragmentsPerPacket) ;
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internal const uint MaxRxFragmentsInRing = ((MaxRxPackets + 1) *
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MaxRxFragmentsPerPacket);
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internal const ChecksumSupport ChecksumSupport =
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ChecksumSupport.AllIp4Recieve | ChecksumSupport.AllIp6Recieve;
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internal const uint IEEE8023FrameBytes = 1518;
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internal const uint MtuBytes = 1514;
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internal const uint PhyAddress = 1;
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private string! cardName;
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private CardType cardType;
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private PciDeviceConfig! pciConfig;
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private IoMemory! ioMemory;
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private IoIrq! irq;
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private Thread irqWorkerThread;
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private bool irqWorkerStop;
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private bool ioRunning;
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private IntelEventRelay eventRelay;
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private EerdRegister! eerdReg;
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private EthernetAddress macAddress;
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private IntelRxRingBuffer! rxRingBuffer;
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private IntelTxRingBuffer! txRingBuffer;
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[NotDelayed]
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internal Intel(IntelResources! res)
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{
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IoMemoryRange imr = (!)res.imr;
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ioMemory = (!) imr.MemoryAtOffset(0, 0x20000, Access.ReadWrite);
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IoIrqRange! iir = (!)res.irq;
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irq = (!) iir.IrqAtOffset(0);
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rxRingBuffer = new IntelRxRingBuffer(MaxRxFragmentsInRing);
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txRingBuffer = new IntelTxRingBuffer(MaxTxFragmentsInRing);
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this.cardName = res.CardName;
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this.cardType = res.CardType;
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PciDeviceConfig! config = (PciDeviceConfig!)IoConfig.GetConfig();
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this.pciConfig = config;
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DebugWriteLine("PCI Control {0:x8} Status {1:x8}",
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__arglist(config.Control, config.Status));
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byte cap = config.Capabilities;
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while (cap != 0 && cap < 0xff) {
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DebugWriteLine("Capability at: {0:x2}", __arglist(cap));
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byte id = config.Read8(cap);
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if (id == 7) {
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DebugWriteLine("PCI-X Command {0:x4} Status {1:x8}",
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__arglist(
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config.Read16(cap + 2) & 0x3f,
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config.Read32(cap + 4)
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)
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);
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}
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else if (id == 5) {
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// MSI capability - only reached if enabled,
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// but usually present.
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DebugWriteLine("MSI Control {0:x4} Address {1:x8}.{2:x8} Data {3:x4}",
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__arglist(config.Read16(cap + 2),
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config.Read32(cap + 8),
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config.Read32(cap + 4),
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config.Read16(cap + 10)
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)
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);
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}
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else {
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DebugWriteLine("Unknown capability {0:x2}", __arglist(id));
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}
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cap = config.Read8(cap + 1);
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}
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eerdReg = new EerdRegister(config.DeviceId);
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base();
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DebugWriteLine("Irq {0}", __arglist(irq.Irq));
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Debug.Assert((config.Control & PciConfig.PCI_ENABLE_BUS_MASTER) != 0);
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Debug.Assert((config.Control & PciConfig.PCI_ENABLE_MEMORY_SPACE) != 0);
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DebugStub.Assert(config.InterruptsEnabled);
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}
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~Intel()
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{
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ReleaseResources();
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Initialisation and finalisation code
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//
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internal void Initialize()
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{
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DebugPrint("Initialising " + DriverName + " Version " + DriverVersion);
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if (!irq.RegisterInterrupt()) {
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DebugStub.Break();
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}
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ResetDevice();
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SetupPhys();
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SetupMac();
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}
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void ReleaseResources()
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{
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DisableInterrupts();
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StopIo();
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irq.ReleaseInterrupt();
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irqWorkerThread = null;
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}
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internal void Shutdown()
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{
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if (irqWorkerThread != null) {
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// XXX This is not the right way to do this.
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DisableInterrupts();
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StopIo();
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}
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}
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internal void StartIo()
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{
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irqWorkerStop = false;
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irqWorkerThread = new Thread(new ThreadStart(this.IrqWorkerMain));
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irqWorkerThread.Start();
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SetupMac();
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EnableInterrupts();
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StartReceiver();
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StartTransmitter();
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this.ioRunning = true;
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}
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internal void StopIo()
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{
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StopTransmitter();
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StopReceiver();
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if (irqWorkerThread != null) {
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// Set stop flag, wake-up irqWorker thread, then wait.
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irqWorkerStop = true;
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irq.Pulse();
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irqWorkerThread.Join();
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irqWorkerThread = null;
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}
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this.ioRunning = false;
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}
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internal void SetEventRelay(IntelEventRelay intelEventRelay)
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{
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eventRelay = intelEventRelay;
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Setup functions
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//
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private void ResetDevice()
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{
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// Disable all interrupts
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DisableInterrupts();
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DebugWriteLine("CTRL pre-device-reset : {0:x8}\n",
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__arglist(Read32(Register.CTRL)));
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Write32(Register.RECV_CTRL, 0);
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Write32(Register.TSMT_CTRL, TsmtCtrlBits.PAD_SHORT_PACKETS);
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Read32(Register.STATUS);
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// Allow pending PCI transactions to complete
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Delay(10);
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// Reset the device
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RegSetBits(Register.CTRL, CtrlBits.RST | CtrlBits.PHY_RST);
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// Wait for 3us before board is really reset
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Delay(3);
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Delay(100);
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Read32(Register.CTRL);
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// Set the control register to the proper initial values,
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// clearing RST and PHY_RST as a side-effect.
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Write32(Register.CTRL, CtrlBits.FD | CtrlBits.ASDE | CtrlBits.SLU);
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while ((Read32(Register.CTRL) & CtrlBits.RST) != 0) {
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DebugWriteLine(".");
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}
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DebugWriteLine("Autonegotiation complete");
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}
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private void SetupPhys()
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{
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if (this.cardType == CardType.I82545GM ) {
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Write32(Register.MDIC, Mdic.MdiRead);
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while ((Read32(Register.MDIC) & Mdic.Ready) == 0);
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uint mdic = Read32(Register.MDIC) & Mdic.DataMask;
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mdic |= Mdic.MdiWrite;
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mdic &= Mdic.PowerMask;
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Write32(Register.MDIC, mdic);
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while ((Read32(Register.MDIC) & Mdic.Ready) == 0);
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DumpPhy();
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uint ctrl = Read32(Register.CTRL);
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ctrl |= CtrlBits.SLU | CtrlBits.ASDE;
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ctrl &= ~(CtrlBits.ILOS | CtrlBits.FRCSPD | CtrlBits.FRCDPLX);
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Write32(Register.CTRL, ctrl);
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Delay(20);
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// Wait for link to come up
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int attempts = 5000;
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while ((MiiRead(PhyAddress, 1) & 0x4) == 0) {
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Delay(1000);
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if (0 == attempts--) {
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DumpPhy();
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DebugStub.Break();
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}
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}
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DumpPhy();
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uint phyCtrl = MiiRead(PhyAddress, 0);
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phyCtrl |= 0x1200; // Enable-AutoNeg + Restart-AutoNeg
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MiiWrite(PhyAddress, 0, phyCtrl);
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uint phyStat;
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attempts = 5000;
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do {
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Delay(1000);
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phyStat = MiiRead(PhyAddress, 1);
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phyStat = MiiRead(PhyAddress, 1);
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} while ((phyStat & 0x20) == 0 && --attempts > 0); // wait for autoneg complete
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DebugStub.Assert((phyStat & 0x20) != 0);
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// Transfer settings from phy to ctrl
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uint phyPssr = MiiRead(PhyAddress, 17);
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ctrl = Read32(Register.CTRL);
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ctrl &= ~(CtrlBits.SPEED | CtrlBits.FD);
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if ((phyPssr & (1 << 13)) != 0) {
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ctrl |= CtrlBits.FD;
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}
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ctrl |= ((phyPssr >> 14) & 3) << 8;
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ctrl |= CtrlBits.FRCSPD | CtrlBits.FRCDPLX;
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Write32(Register.CTRL, ctrl);
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Delay(1000000);
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DumpPhy();
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}
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else if (this.cardType == CardType.I82541PI) {
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// Use Internal Phys mode (SerDes is not possible for some 8254x cards)
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Write32BitRange(Register.CTRL_EXT,
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CtrlExtBits.LINK_MODE_PHYS,
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CtrlExtBits.LINK_MODE_LO_BIT,
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CtrlExtBits.LINK_MODE_HI_BIT);
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}
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// We don't want flow control
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Write32(Register.FCAL, 0x0);
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Write32(Register.FCAH, 0x0);
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Write32(Register.FCT, 0x0);
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Write32(Register.FCTTV, 0x0);
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}
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private void SetupMac()
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{
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uint ral, rah;
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// Setup our Ethernet address
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macAddress = GetMacFromEeprom();
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DebugPrint("Setting Ethernet Mac Address to {0:s}\n",
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__arglist(macAddress.ToString()));
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GetMacHiLow(out ral, out rah, macAddress);
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rah = rah | RahRegister.ADDRESS_VALID;
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Write32(Register.RAL0, ral);
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Write32(Register.RAH0, rah);
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// Clear the mutlicast table array
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for (uint i = 0; i < MtaRegister.MTA_LENGTH; i++)
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{
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Write32(Register.MTA_START + (4*i), 0);
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}
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// Setup Descriptor buffers for rx
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ResetRxRingBuffer();
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// Setup Receiever Control flags
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Write32(Register.RECV_CTRL, (RecvCtrlBits.BROADCAST_ACCEPT |
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RecvCtrlBits.STRIP_CRC |
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RecvCtrlBits.LOOPBACK_MODE_DISABLE |
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RecvCtrlBits.MULTICAST_OFFSET_47_36 |
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RecvCtrlBits.BUFFER_SIZE_2KB |
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RecvCtrlBits.RECV_DESC_THRESHOLD_QUARTER));
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// Note: If MTU ever changes (e.g. for jumbo frames), the
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// recv buffer size will need to be increased.
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// Setup the rx interrupt delay
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Write32(Register.RECV_DELAY_TIMER, RxDelayTimers.RECV_DELAY_TIMER);
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Write32(Register.RECV_INT_ABS_TIMER, RxDelayTimers.RECV_ABSOLUTE_TIMER);
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// Enable IP and TCP checksum calculation offloading
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Write32(Register.RECV_CHECKSUM, (RecvChecksumBits.IP_CHECKSUM_ENABLE |
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RecvChecksumBits.TCP_CHECKSUM_ENABLE |
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RecvChecksumBits.IP6_CHECKSUM_ENABLE));
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// Setup Descriptor buffers for tx
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ResetTxRingBuffer();
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// Setup Transmit Control flags
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Write32(Register.TSMT_CTRL,
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TsmtCtrlBits.PAD_SHORT_PACKETS |
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|
|
TsmtCtrlBits.COLL_THRESHOLD_DEFAULT |
|
||
|
|
TsmtCtrlBits.COLL_DISTANCE_DEFAULT);
|
||
|
|
|
||
|
|
// Setup Transmit Inter Frame Gap
|
||
|
|
Write32(Register.TSMT_IPG, TsmtIpg.DEFAULT_IPG);
|
||
|
|
|
||
|
|
// TODO enable transmit checksum offloading
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Helper functions
|
||
|
|
//
|
||
|
|
internal void GetMacHiLow(out uint addr_low,
|
||
|
|
out uint addr_hi,
|
||
|
|
EthernetAddress mac)
|
||
|
|
{
|
||
|
|
byte[]! macBytes = mac.GetAddressBytes();
|
||
|
|
addr_hi = (uint) ((macBytes[5] << 8) |
|
||
|
|
(macBytes[4]));
|
||
|
|
addr_low = (uint) ((macBytes[3] << 24) |
|
||
|
|
(macBytes[2] << 16) |
|
||
|
|
(macBytes[1] << 8) |
|
||
|
|
(macBytes[0]));
|
||
|
|
}
|
||
|
|
|
||
|
|
internal EthernetAddress GetMacFromEeprom()
|
||
|
|
{
|
||
|
|
ushort eepromData;
|
||
|
|
|
||
|
|
byte[] macBytes = new byte[6];
|
||
|
|
|
||
|
|
// Mac address is in reverse byte order in the EEPROM
|
||
|
|
eepromData = ReadEepromWord(0);
|
||
|
|
macBytes[0] = (byte) (eepromData & 0xff);
|
||
|
|
macBytes[1] = (byte) (eepromData >> 8);
|
||
|
|
|
||
|
|
eepromData = ReadEepromWord(1);
|
||
|
|
macBytes[2] = (byte) (eepromData & 0xff);
|
||
|
|
macBytes[3] = (byte) (eepromData >> 8);
|
||
|
|
|
||
|
|
eepromData = ReadEepromWord(2);
|
||
|
|
macBytes[4] = (byte) (eepromData & 0xff);
|
||
|
|
macBytes[5] = (byte) (eepromData >> 8);
|
||
|
|
|
||
|
|
return new EthernetAddress(macBytes);
|
||
|
|
}
|
||
|
|
|
||
|
|
private ushort ReadEepromWord(ushort eepromAddress)
|
||
|
|
{
|
||
|
|
uint eepromRead;
|
||
|
|
|
||
|
|
// Write address required
|
||
|
|
uint writeVal = (EerdRegister.Start |
|
||
|
|
((uint) eepromAddress << eerdReg.AddressShift));
|
||
|
|
|
||
|
|
Write32(Register.EERD, writeVal);
|
||
|
|
|
||
|
|
// wait until read has completed
|
||
|
|
do {
|
||
|
|
eepromRead = Read32(Register.EERD);
|
||
|
|
} while ((eepromRead & eerdReg.Done) == 0);
|
||
|
|
|
||
|
|
// return data value
|
||
|
|
return (ushort) (eepromRead >> EerdRegister.DataShift);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Interrupt Handling
|
||
|
|
//
|
||
|
|
internal void EnableInterrupts()
|
||
|
|
{
|
||
|
|
// Clear existing interrupts
|
||
|
|
Write32(Register.IMC, 0xffffffff);
|
||
|
|
Read32(Register.ICR);
|
||
|
|
|
||
|
|
// Set interrupts we are interested in
|
||
|
|
RegSetBits(Register.IMS, (InterruptMasks.RXT0 | InterruptMasks.RXO |
|
||
|
|
InterruptMasks.RXDMT0 |
|
||
|
|
InterruptMasks.LSC | InterruptMasks.TXQE |
|
||
|
|
InterruptMasks.TXDW));
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void DisableInterrupts()
|
||
|
|
{
|
||
|
|
// Clear existing interrupts
|
||
|
|
Write32(Register.IMC, 0xffffffff);
|
||
|
|
Read32(Register.ICR);
|
||
|
|
}
|
||
|
|
|
||
|
|
private bool HandleInterrupts(uint intrCause)
|
||
|
|
{
|
||
|
|
if (intrCause == 0) {
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
NicEventType ev = NicEventType.NoEvent;
|
||
|
|
|
||
|
|
if ((intrCause & InterruptMasks.LSC) != 0) {
|
||
|
|
DebugPrint("Link Status Change\n");
|
||
|
|
ev |= NicEventType.LinkEvent;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((intrCause & InterruptMasks.RXSEQ) != 0) {
|
||
|
|
DebugPrint("Sequence Error\n");
|
||
|
|
ev |= NicEventType.LinkEvent;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (((InterruptMasks.RXT0 |
|
||
|
|
InterruptMasks.RXO |
|
||
|
|
InterruptMasks.RXDMT0) & intrCause) != 0) {
|
||
|
|
ev |= NicEventType.ReceiveEvent;
|
||
|
|
}
|
||
|
|
|
||
|
|
// no transmit interupts are set, check rxbuffer to see
|
||
|
|
// if any packets have been sent since last time
|
||
|
|
if (txRingBuffer.NewTransmitEvent()) {
|
||
|
|
ev |= NicEventType.TransmitEvent;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (eventRelay != null) {
|
||
|
|
eventRelay.ForwardEvent(ev);
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
private void IrqWorkerMain()
|
||
|
|
{
|
||
|
|
DebugPrint(
|
||
|
|
"Intel {0} Ethernet Driver irq worker thread started.\n",
|
||
|
|
__arglist(this.cardName)
|
||
|
|
);
|
||
|
|
|
||
|
|
while (irqWorkerStop == false) {
|
||
|
|
irq.WaitForInterrupt();
|
||
|
|
uint icr = Read32(Register.ICR);
|
||
|
|
HandleInterrupts(icr);
|
||
|
|
irq.AckInterrupt();
|
||
|
|
}
|
||
|
|
|
||
|
|
DisableInterrupts();
|
||
|
|
DebugPrint(
|
||
|
|
"Intel {0} Ethernet Driver irq worker thread stopped.\n",
|
||
|
|
__arglist(this.cardName)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Rx buffer operations
|
||
|
|
//
|
||
|
|
|
||
|
|
internal void PopulateRecvBuffer(PacketFifo*! in ExHeap fromUser)
|
||
|
|
{
|
||
|
|
lock (rxRingBuffer) {
|
||
|
|
while (fromUser->Count > 0) {
|
||
|
|
rxRingBuffer.LockedPushRecvBuffer(fromUser->Pop());
|
||
|
|
}
|
||
|
|
Write32(Register.RECV_DESC_TAIL, rxRingBuffer.Head);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void DrainRecvBuffer(PacketFifo*! in ExHeap toUser)
|
||
|
|
{
|
||
|
|
lock (rxRingBuffer) {
|
||
|
|
rxRingBuffer.LockedDrainRecvBuffer(toUser);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private void ResetRxRingBuffer()
|
||
|
|
{
|
||
|
|
ulong descBase;
|
||
|
|
uint descBaseLo, descBaseHi;
|
||
|
|
|
||
|
|
rxRingBuffer.Reset();
|
||
|
|
descBase = rxRingBuffer.BaseAddress.ToUInt64();
|
||
|
|
descBaseLo = (uint)(0xffffffff & descBase);
|
||
|
|
descBaseHi = (uint) (0xffffffff & (descBase >> 32));
|
||
|
|
Write32(Register.RECV_DESC_BASE_LO, ByteOrder.HostToLittleEndian(descBaseLo));
|
||
|
|
Write32(Register.RECV_DESC_BASE_HI, ByteOrder.HostToLittleEndian(descBaseHi));
|
||
|
|
Write32(Register.RECV_DESC_LENGTH, ByteOrder.HostToLittleEndian(rxRingBuffer.DescLength));
|
||
|
|
Write32(Register.RECV_DESC_HEAD, ByteOrder.HostToLittleEndian(rxRingBuffer.Head));
|
||
|
|
Write32(Register.RECV_DESC_TAIL, ByteOrder.HostToLittleEndian(rxRingBuffer.Tail));
|
||
|
|
}
|
||
|
|
|
||
|
|
private void StartReceiver()
|
||
|
|
{
|
||
|
|
ResetRxRingBuffer();
|
||
|
|
RegSetBits(Register.RECV_CTRL, RecvCtrlBits.RECV_ENABLE);
|
||
|
|
|
||
|
|
DebugPrint("Receiver Enabled.\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
private void StopReceiver()
|
||
|
|
{
|
||
|
|
RegClrBits(Register.RECV_CTRL, RecvCtrlBits.RECV_ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Tx buffer operations
|
||
|
|
//
|
||
|
|
|
||
|
|
internal void PopulateTsmtBuffer(PacketFifo*! in ExHeap fromUser)
|
||
|
|
{
|
||
|
|
DebugStub.Assert(this.ioRunning);
|
||
|
|
|
||
|
|
// since no transmit interrupts are sent, we must check for
|
||
|
|
// transmission events here
|
||
|
|
if (txRingBuffer.NewTransmitEvent()) {
|
||
|
|
NicEventType ev = NicEventType.TransmitEvent;
|
||
|
|
if (eventRelay != null) {
|
||
|
|
eventRelay.ForwardEvent(ev);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
lock (txRingBuffer) {
|
||
|
|
while (fromUser->Count > 0) {
|
||
|
|
Packet*! in ExHeap packet = fromUser->Pop();
|
||
|
|
txRingBuffer.LockedPushTsmtBuffer(packet);
|
||
|
|
}
|
||
|
|
// update hardware tail pointer
|
||
|
|
// so that hardware knows it has new packets to transmit
|
||
|
|
Write32(Register.TSMT_DESC_TAIL, txRingBuffer.Head); // sw head is hw tail
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void DrainTsmtBuffer(PacketFifo*! in ExHeap toUser)
|
||
|
|
{
|
||
|
|
lock (txRingBuffer) {
|
||
|
|
txRingBuffer.LockedDrainTsmtBuffer(toUser);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private void ResetTxRingBuffer()
|
||
|
|
{
|
||
|
|
ulong descBase;
|
||
|
|
uint descBaseLo, descBaseHi;
|
||
|
|
|
||
|
|
txRingBuffer.Reset();
|
||
|
|
descBase = txRingBuffer.BaseAddress.ToUInt64();
|
||
|
|
descBaseLo = (uint)(0xffffffff & descBase);
|
||
|
|
descBaseHi = (uint) (0xffffffff & (descBase >> 32));
|
||
|
|
Write32(Register.TSMT_DESC_BASE_LO, ByteOrder.HostToLittleEndian(descBaseLo));
|
||
|
|
Write32(Register.TSMT_DESC_BASE_HI, ByteOrder.HostToLittleEndian(descBaseHi));
|
||
|
|
Write32(Register.TSMT_DESC_LENGTH, ByteOrder.HostToLittleEndian(txRingBuffer.DescLength));
|
||
|
|
Write32(Register.TSMT_DESC_HEAD, ByteOrder.HostToLittleEndian(txRingBuffer.Head));
|
||
|
|
Write32(Register.TSMT_DESC_TAIL, ByteOrder.HostToLittleEndian(txRingBuffer.Tail));
|
||
|
|
}
|
||
|
|
|
||
|
|
private void StartTransmitter()
|
||
|
|
{
|
||
|
|
ResetTxRingBuffer();
|
||
|
|
RegSetBits(Register.TSMT_CTRL, TsmtCtrlBits.TSMT_ENABLE);
|
||
|
|
|
||
|
|
DebugPrint("Transmitter Enabled.\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
private void StopTransmitter()
|
||
|
|
{
|
||
|
|
RegClrBits(Register.TSMT_CTRL, TsmtCtrlBits.TSMT_ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Driver Details
|
||
|
|
//
|
||
|
|
|
||
|
|
internal string! DriverName
|
||
|
|
{
|
||
|
|
get { return string.Format("Intel {0} Ethernet Driver", this.cardName); }
|
||
|
|
}
|
||
|
|
|
||
|
|
internal string! DriverVersion
|
||
|
|
{
|
||
|
|
get { return "0.1"; }
|
||
|
|
}
|
||
|
|
|
||
|
|
internal EthernetAddress getMacAddress
|
||
|
|
{
|
||
|
|
get { return macAddress; }
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// MII
|
||
|
|
//
|
||
|
|
|
||
|
|
private uint MiiRead(uint phy, uint register)
|
||
|
|
{
|
||
|
|
uint mdic = (((phy & Mdic.PhyMask) << Mdic.PhyRoll) |
|
||
|
|
((register & Mdic.RegMask) << Mdic.RegRoll) |
|
||
|
|
Mdic.MdiRead);
|
||
|
|
|
||
|
|
Write32(Register.MDIC, mdic);
|
||
|
|
do {
|
||
|
|
mdic = Read32(Register.MDIC);
|
||
|
|
DebugStub.Assert((mdic & Mdic.Error) == 0);
|
||
|
|
} while ((mdic & Mdic.Ready) == 0);
|
||
|
|
|
||
|
|
return mdic & Mdic.DataMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
private uint MiiWrite(uint phy, uint register, uint value)
|
||
|
|
{
|
||
|
|
DebugStub.Assert((value & ~Mdic.DataMask) == 0);
|
||
|
|
|
||
|
|
uint mdic = (((phy & Mdic.PhyMask) << Mdic.PhyRoll) |
|
||
|
|
((register & Mdic.RegMask) << Mdic.RegRoll) |
|
||
|
|
Mdic.MdiWrite);
|
||
|
|
|
||
|
|
mdic |= (uint)value;
|
||
|
|
|
||
|
|
Write32(Register.MDIC, mdic);
|
||
|
|
do {
|
||
|
|
mdic = Read32(Register.MDIC);
|
||
|
|
DebugStub.Assert((mdic & Mdic.Error) == 0);
|
||
|
|
} while ((mdic & Mdic.Ready) == 0);
|
||
|
|
|
||
|
|
return mdic & Mdic.DataMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Register accessors / modifiers / utilities
|
||
|
|
//
|
||
|
|
|
||
|
|
private uint Read32(uint offset)
|
||
|
|
{
|
||
|
|
return ioMemory.Read32((int) offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
private void Write32(uint offset, uint value)
|
||
|
|
{
|
||
|
|
ioMemory.Write32((int) offset, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
private void Write32BitRange(uint offset,
|
||
|
|
uint new_val,
|
||
|
|
int hiBit,
|
||
|
|
int loBit)
|
||
|
|
{
|
||
|
|
uint write_val = SetValueBits(Read32(offset), new_val, hiBit, loBit);
|
||
|
|
Write32(offset, write_val);
|
||
|
|
}
|
||
|
|
|
||
|
|
private void RegSetBits(int offset, uint bits)
|
||
|
|
{
|
||
|
|
ioMemory.Write32(offset, ioMemory.Read32(offset) | bits);
|
||
|
|
}
|
||
|
|
|
||
|
|
private void RegClrBits(int offset, uint bits)
|
||
|
|
{
|
||
|
|
ioMemory.Write32(offset, ioMemory.Read32(offset) & ~bits);
|
||
|
|
}
|
||
|
|
|
||
|
|
private uint SetValueBits(uint value,
|
||
|
|
uint bits,
|
||
|
|
int hiBit,
|
||
|
|
int loBit)
|
||
|
|
{
|
||
|
|
int width = (hiBit - loBit) + 1;
|
||
|
|
uint mask = (1u << width) - 1u;
|
||
|
|
bits = (bits & mask);
|
||
|
|
value &= ~(mask << loBit);
|
||
|
|
value |= bits << loBit;
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
|
||
|
|
private void SetBit(ref uint value, int bit)
|
||
|
|
{
|
||
|
|
value = value | (1u << bit);
|
||
|
|
}
|
||
|
|
|
||
|
|
private void ClearBit(ref uint value, int bit)
|
||
|
|
{
|
||
|
|
value = value & ~(1u << bit);
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void Delay(int us)
|
||
|
|
{
|
||
|
|
long expiry = ProcessService.GetUpTime().Ticks + (us * 10);
|
||
|
|
while (ProcessService.GetUpTime().Ticks < expiry);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Debug Helper Functions
|
||
|
|
//
|
||
|
|
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
internal static void DebugPrint(string format, __arglist)
|
||
|
|
{
|
||
|
|
DebugStub.Print(format, new ArgIterator(__arglist));
|
||
|
|
}
|
||
|
|
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
internal static void DebugPrint(string format)
|
||
|
|
{
|
||
|
|
DebugStub.Print(format);
|
||
|
|
}
|
||
|
|
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
internal static void DebugWriteLine(string format, __arglist)
|
||
|
|
{
|
||
|
|
DebugStub.WriteLine(format, new ArgIterator(__arglist));
|
||
|
|
}
|
||
|
|
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
internal static void DebugWriteLine(string format)
|
||
|
|
{
|
||
|
|
DebugStub.WriteLine(format);
|
||
|
|
}
|
||
|
|
|
||
|
|
///////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Debugging methods
|
||
|
|
//
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
private void DumpBufferDebugRegisters()
|
||
|
|
{
|
||
|
|
// TODO, uses Tracing log
|
||
|
|
DebugPrint("Device Control {0:x8} Device Status {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.CTRL),
|
||
|
|
Read32(Register.STATUS)));
|
||
|
|
|
||
|
|
DebugPrint("PCI Status {0:x4}", __arglist(this.pciConfig.Status));
|
||
|
|
|
||
|
|
DebugPrint("Recv Control {0:x8} Tsmt Control {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.RECV_CTRL),
|
||
|
|
Read32(Register.TSMT_CTRL)));
|
||
|
|
|
||
|
|
DebugPrint("RDTR {0:x8} RADV {1:x8}\n",
|
||
|
|
__arglist(Read32(0x2820), Read32(0x282c)));
|
||
|
|
|
||
|
|
DebugPrint("Total Transmit {0:x8} Total Received {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.TOTAL_TSMT_PACKETS),
|
||
|
|
Read32(Register.TOTAL_RECV_PACKETS)));
|
||
|
|
|
||
|
|
DebugPrint("Interrupt Mask {0:x8} Rx Error Count {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.IMS),
|
||
|
|
Read32(Register.RX_ERR_COUNT)));
|
||
|
|
|
||
|
|
DebugPrint("Recv Addr High {0:x8} Recv Addr Low {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.RAH0),
|
||
|
|
Read32(Register.RAL0)));
|
||
|
|
|
||
|
|
DebugPrint("Recv Desc Head {0:x8} Recv Desc Tail {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.RECV_DESC_HEAD),
|
||
|
|
Read32(Register.RECV_DESC_TAIL)));
|
||
|
|
|
||
|
|
DebugPrint("Tsmt Desc Head {0:x8} Tsmt Desc Tail {1:x8}\n",
|
||
|
|
__arglist(Read32(Register.TSMT_DESC_HEAD),
|
||
|
|
Read32(Register.TSMT_DESC_TAIL)));
|
||
|
|
}
|
||
|
|
|
||
|
|
[Conditional("DEBUG_INTEL")]
|
||
|
|
private void DumpPhy()
|
||
|
|
{
|
||
|
|
for (uint i = 0; i < 32; i += 8) {
|
||
|
|
DebugWriteLine("PHY {0:x4} : {1:x4} {2:x4} {3:x4} {4:x4} {5:x4} {6:x4} {7:x4} {8:x4}",
|
||
|
|
__arglist(i,
|
||
|
|
MiiRead(PhyAddress, i + 0),
|
||
|
|
MiiRead(PhyAddress, i + 1),
|
||
|
|
MiiRead(PhyAddress, i + 2),
|
||
|
|
MiiRead(PhyAddress, i + 3),
|
||
|
|
MiiRead(PhyAddress, i + 4),
|
||
|
|
MiiRead(PhyAddress, i + 5),
|
||
|
|
MiiRead(PhyAddress, i + 6),
|
||
|
|
MiiRead(PhyAddress, i + 7))
|
||
|
|
);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if DEBUG_INTEL
|
||
|
|
// Occasionally helpful when debugging.
|
||
|
|
|
||
|
|
Thread statsThread = null;
|
||
|
|
|
||
|
|
internal void StartStatistics()
|
||
|
|
{
|
||
|
|
DebugStub.Assert(statsThread == null);
|
||
|
|
statsThread = new Thread(new ThreadStart(this.StatisticsMain));
|
||
|
|
statsThread.Start();
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void ReportChanges(uint[]! now)
|
||
|
|
{
|
||
|
|
DebugWriteLine("Changes.");
|
||
|
|
for (int i = 0; i < now.Length; i++) {
|
||
|
|
if (now[i] != 0) {
|
||
|
|
DebugWriteLine("{0} [0x40{1:x1}] -> {2}",
|
||
|
|
__arglist(i, i * 4, now[i]));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
rxRingBuffer.Dump();
|
||
|
|
DebugWriteLine("Rx head {0:x8} tail {1:x8}",
|
||
|
|
__arglist(Read32(Register.RECV_DESC_HEAD),
|
||
|
|
Read32(Register.RECV_DESC_TAIL)));
|
||
|
|
DebugWriteLine("ICS = {0:x8} ICR = {1:x8}",
|
||
|
|
__arglist(Read32(Register.ICS),
|
||
|
|
Read32(Register.ICR)));
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void StatisticsMain()
|
||
|
|
{
|
||
|
|
uint []! counters1 = new uint[64];
|
||
|
|
|
||
|
|
for (;;) {
|
||
|
|
Thread.Sleep(TimeSpan.FromSeconds(10));
|
||
|
|
GetStatistics(counters1);
|
||
|
|
ReportChanges(counters1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
internal void GetStatistics(uint []! counters)
|
||
|
|
{
|
||
|
|
for (uint i = 0; i < counters.Length; i++) {
|
||
|
|
counters[i] = Read32(0x4000 + i * 4);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|