438 lines
13 KiB
NASM
438 lines
13 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; basic_f.s
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;
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; Copyright (C) Advanced RISC Machines Limited, 1994. All rights reserved.
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;
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; RCS Revision: 1
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; Checkin Date: 2007/06/29 02:59:16
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; Revising Author
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; Basic floating point functions
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;
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; Fixed == and != compares to be IEEE-754 compliant when input QNaNs.
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; No exceptions are raised when only QNaNs are the only NaNs input to
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; == and !=. Moved NaN detection and exception raising here.
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; Removed unnecessary macros for compares that return results in flags.
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; Added WindowsCE SEH mechanism support.
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; Renamed routines.
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;
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LOC_SIZE EQU 0x18
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OrgOp1l EQU 0x14
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OrgOp2l EQU 0x10
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ExDResl EQU 0x08
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ExOp2l EQU 0x00
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NewResl EQU 0x10
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GET fpe.asm
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GET kxarm.inc
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;This code is very similar to the "double" versions. The documentation isn't
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;extensively repeated. Refer to basic_d.s for further documentation.
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;==============================================================================
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; Compare.
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;
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; Timing:
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; Flags: 7 (pos), 11 (false NaN), 9 (neg), 13 (false NaN) SA1.1 cycles
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; Others: 9 / 13 / 11 / 15
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;==============================================================================
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MACRO
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CmpReturn $cc
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MOV a1, #0
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MOV$cc a1, #1
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ADD sp, sp, #LOC_SIZE
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr}
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BX lr
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ELSE
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LDMFD sp!, {pc}
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ENDIF
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MEND
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MACRO
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$lab FloatCompare $cc, $NaN_lab
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ASSERT "$cc"="LO":LOR:"$cc"="LS":LOR:"$cc"="HS":LOR:"$cc"="HI":LOR:"$cc"="EQ":LOR:"$cc"="NE"
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NESTED_ENTRY $lab
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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ORRS tmp, fOP1, fOP2 ; separate into opnd1/2 both positive, or one negative
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BMI $lab._negative
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CMN tmp, #1 << 23 ; check whether operands might be infinite/NaN
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BMI $lab._NaN_check_pos
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CMP fOP1, fOP2
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CmpReturn $cc
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$lab._NaN_check_pos ; opnd1/2 might be inf/NaNs - now do the real check
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CMN fOP1, #1 << 23 ; these get about 9% false hits - overhead 4 cycles
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CMNPL fOP2, #1 << 23
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BMI $lab._Inf_or_NaN_pos
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$lab._cmp_pos
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CMP fOP1, fOP2
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CmpReturn $cc
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$lab._Inf_or_NaN_pos ; at least one operand infinite or NaN - filter out infinities
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MOV tmp, #1 << 24
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CMN tmp, fOP1, LSL #1
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CMNLS tmp, fOP2, LSL #1
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BLS $lab._cmp_pos ; no NaN - continue compare
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B $NaN_lab
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$lab._negative ; at least one negative operand
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CMN tmp, #1 << 23
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BPL $lab._NaN_check_neg
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MOVS tmp, tmp, LSL #1 ; check -0 == 0 (CS & EQ -> HS and LS)
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CMPNE fOP2, fOP1
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CmpReturn $cc
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$lab._NaN_check_neg ; opnd1/2 might be inf/NaNs - now do the real check
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MOV tmp, #1 << 24 ; these get about 9% false hits - overhead 4 cycles
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CMN tmp, fOP1, LSL #1
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CMNLS tmp, fOP2, LSL #1
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BHI $NaN_lab
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CMP fOP2, fOP1 ; -0 == 0 check not needed...
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CmpReturn $cc
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MEND
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;==============================================================================
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;Invalid Operation checking (NaNs on compares)
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;;
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IMPORT FPE_Raise
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;;
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;; NANs on compares <, >, <=, and >=
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;;
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;; SNANs and QNANs both raise the invalid operation exception, so we don't
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;; care which kind of NAN we get. This is because if we get an SNAN or SNANs,
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;; we raise the invalid operation exception. If we get a QNAN or QNANs, we
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;; have an unordered compare and must also raise the invalid operation
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;; exception.
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;;
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;; Register usage on entry:
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;; r0 - Arg1
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;; r1 - Arg2
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;; r14 - available for scratch
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;; All others have normal usage semantics.
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;;
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MACRO
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$l FCmpNaN $Filter_lab
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$l STR r1, [sp, #ExOp2l] ;; Push Arg2
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MOV r3, #_FpCompareUnordered ;; Load default result
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STR r3, [sp, #ExDResl] ;; Push default result
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MOV r2, r0 ;; Arg1
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MOV r1, #IVO_bit ;; ExInfo: InvalidOp,
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ORR r1, r1, #_FpCmpS ;; float compare
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ADD r0, sp, #NewResl ;; Pointer to result
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CALL FPE_Raise ;; Deal with exception information
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ;; Load return value
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ADD sp, sp, #LOC_SIZE ;; Retore stack
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;;
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;; Register usage:
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;;
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;; r0 - Result from exception handler
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;;
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;; We must now examine the result from the exception handler and change it
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;; to TRUE or FALSE, depending on the operation. After changing the result,
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;; we return to the caller of the FP double compare routine.
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;;
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B $Filter_lab
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MEND
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;;
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;; NANs on compares == and !=
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;;
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;; SNANs and QNANs are treated differently for == and !=. If we get an SNAN
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;; or SNANs, we must raise the invalid operation exception. If we only have
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;; a QNAN or QNANs, then we simply return false and true for == and !=,
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;; respectively. Unordered comparisions for == and != do not raise the
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;; invalid operation exception.
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;;
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;; Register usage on entry:
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;; r0 - Arg1
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;; r1 - Arg2
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;; r14 - available for scratch
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;; All others have normal usage semantics.
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;;
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MACRO
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$l FCmpSNaN $Filter_lab
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$l MOV r14, r0, LSL #1 ;; Extract exponent from Arg1
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MOV r14, r14, LSR #24 ;; ...
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CMP r14, #0xFF ;; Arg1.exponent == 0xFF?
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BNE $l.checkArg2 ;; Arg1 not a NaN so check Arg2
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MOVS r14, r0, LSL #9 ;; Arg1.Mantissa bits set?
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BEQ $l.checkArg2 ;; Arg1 not a NaN so check Arg2
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TST r0, #fSignalBit ;; Check if SNAN
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BEQ $l.SNaN ;; If high mant. bit clear, SNaN
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$l.checkArg2
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MOV r14, r1, LSL #1 ;; Extract exponent from Arg2
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MOV r14, r14, LSR #24 ;; ...
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CMP r14, #0xFF ;; Arg2.exponent == 0xFF?
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BNE $l.cmpUnordered ;; Arg2 not a NaN so Arg1 is a QNaN
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MOVS r14, r1, LSL #9 ;; Arg2.Mantissa bits set?
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BEQ $l.cmpUnordered ;; Arg2 not a NaN so Arg1 is a QNaN
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TST r1, #fSignalBit ;; Check if SNAN
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BEQ $l.SNaN ;; If high mant. bit clear, SNaN
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$l.cmpUnordered
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MOV r0, #_FpCompareUnordered ;; Have an unordered compare so
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B $Filter_lab ;; don't raise an exception
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$l.SNaN
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STR r1, [sp, #ExOp2l] ;; Push Arg2
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MOV r3, #_FpCompareUnordered ;; Load default result
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STR r3, [sp, #ExDResl] ;; Push default result
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MOV r2, r0 ;; Arg1
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MOV r1, #IVO_bit ;; ExInfo: InvalidOp,
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ORR r1, r1, #_FpCmpS ;; float compare
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ADD r0, sp, #NewResl ;; Pointer to result
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CALL FPE_Raise ;; Deal with exception information
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ;; Load return value
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;;
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;; Register usage:
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;;
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;; r0 - Result from exception handler
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;;
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;; We must now examine the result from the exception handler and change it
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;; to TRUE or FALSE, depending on the operation. After changing the result,
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;; we return to the caller of the FP double compare routine.
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;;
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B $Filter_lab
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MEND
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;==============================================================================
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; Equality
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[ :DEF: eq_s
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Export __eqs
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AREA |.text|, CODE, READONLY
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__eqs FloatCompare EQ, __eqs_NaN
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__eqs_NaN FCmpSNaN __eqs_Filter
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__eqs_Filter
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CMP r0, #_FpCompareEqual ;; Check if compared ==
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MOVEQ r0, #1 ;; If did, return true
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MOVNE r0, #0 ;; else return false
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ADD sp, sp, #0x18 ;; Pop extra arg passing space
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr} ;; Return
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BX lr
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ELSE
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LDMIA sp!, {pc} ;; Return
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ENDIF
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ENTRY_END __eqs
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]
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;==============================================================================
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;Inequality
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[ :DEF: neq_s
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Export __nes
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AREA |.text|, CODE, READONLY
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__nes FloatCompare NE, __nes_NaN
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__nes_NaN FCmpSNaN __nes_Filter
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__nes_Filter
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CMP r0, #_FpCompareEqual ;; Check if compared ==
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MOVEQ r0, #0 ;; If did, return false
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MOVNE r0, #1 ;; else return true
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ADD sp, sp, #0x18 ;; Pop extra arg passing space
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr} ;; Return
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BX lr
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ELSE
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LDMIA sp!, {pc} ;; Return
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ENDIF
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ENTRY_END __nes
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]
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;==============================================================================
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;Less Than
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[ :DEF: ls_s
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Export __lts
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AREA |.text|, CODE, READONLY
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__lts FloatCompare LO, __lts_NaN
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__lts_NaN FCmpNaN __lts_Filter
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__lts_Filter
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CMP r0, #_FpCompareLess ;; Check if compared <
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MOVEQ r0, #1 ;; If did, return true
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MOVNE r0, #0 ;; else return false
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr} ;; Return
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BX lr
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ELSE
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LDMIA sp!, {pc} ;; Return
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ENDIF
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ENTRY_END __lts
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]
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;==============================================================================
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;Less Than or Equal
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[ :DEF: leq_s
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Export __les
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AREA |.text|, CODE, READONLY
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__les FloatCompare LS, __les_NaN
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__les_NaN FCmpNaN __les_Filter
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__les_Filter
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CMP r0, #_FpCompareLess ;; Check if compared <
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MOVEQ r0, #1 ;; If did,
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BEQ __les_Filter_end ;; return true
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CMP r0, #_FpCompareEqual ;; Check if compared ==
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MOVEQ r0, #1 ;; If did, return true
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MOVNE r0, #0 ;; else return false
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__les_Filter_end
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr} ;; Return
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BX lr
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ELSE
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LDMIA sp!, {pc} ;; Return
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ENDIF
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ENTRY_END __les
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]
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;==============================================================================
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;Greater Than
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[ :DEF: gr_s
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Export __gts
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AREA |.text|, CODE, READONLY
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__gts FloatCompare HI, __gts_NaN
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__gts_NaN FCmpNaN __gts_Filter
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__gts_Filter
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CMP r0, #_FpCompareGreater ;; Check if compared >
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MOVEQ r0, #1 ;; If did, return true
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MOVNE r0, #0 ;; else return false
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr} ;; Return
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BX lr
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ELSE
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LDMIA sp!, {pc} ;; Return
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
ENTRY_END __gts
|
||
|
|
]
|
||
|
|
|
||
|
|
;==============================================================================
|
||
|
|
;Greater Than or Equal
|
||
|
|
|
||
|
|
[ :DEF: geq_s
|
||
|
|
|
||
|
|
Export __ges
|
||
|
|
|
||
|
|
AREA |.text|, CODE, READONLY
|
||
|
|
|
||
|
|
__ges FloatCompare HS, __ges_NaN
|
||
|
|
|
||
|
|
__ges_NaN FCmpNaN __ges_Filter
|
||
|
|
|
||
|
|
__ges_Filter
|
||
|
|
CMP r0, #_FpCompareGreater ;; Check if compared >
|
||
|
|
MOVEQ r0, #1 ;; If did,
|
||
|
|
BEQ __ges_Filter_end ;; return true
|
||
|
|
CMP r0, #_FpCompareEqual ;; Check if compared ==
|
||
|
|
MOVEQ r0, #1 ;; If did, return true
|
||
|
|
MOVNE r0, #0 ;; else return false
|
||
|
|
__ges_Filter_end
|
||
|
|
IF Interworking :LOR: Thumbing
|
||
|
|
LDMIA sp!, {lr} ;; Return
|
||
|
|
BX lr
|
||
|
|
ELSE
|
||
|
|
LDMIA sp!, {pc} ;; Return
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
ENTRY_END __ges
|
||
|
|
]
|
||
|
|
|
||
|
|
;==============================================================================
|
||
|
|
|
||
|
|
END
|