635 lines
22 KiB
NASM
635 lines
22 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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GBLL add_s
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GET veneer_d.asm
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END
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;;;; THE BELOW ROUTINE SHOULD WORK, BUT THE ARM ROUTINES SHOULD BE FASTER.
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;
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; Translated to ARM from SH3 FP emulation routines.
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;
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; __addd Double precision floating point addition.
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; Input:
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; r0 - Arg1.low
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; r1 - Arg1.high
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; r2 - Arg2.low
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; r3 - Arg2.high
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; Output:
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; r0 - Result.low
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; r1 - Result.high
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;
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; Note:
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; If any FP exceptions are enabled, this routine may raise an exception.
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;
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;
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; IEEE DOUBLE FORMAT
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;
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; 8 BYTES (LONG WORD * 2)
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; 63 62 52 51 0
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; +-+-----------+----------------------------------------------------+
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; |s| e(11) | m(52) |
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; +-+-----------+----------------------------------------------------+
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; ^ point
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;
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; INFINITY NUMBER : e = 2047 m = 0
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; ZERO : e = 0 m = 0
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; NaN : e = 2047 m != 0
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; DENORMAL NUMBER : e = 0 m != 0
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;
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GET fpe.asm
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Export __addd
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Export __subd
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IMPORT FPE_Raise
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AREA |.text|, CODE, READONLY
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CARRY_CHECK EQU 0x01000000
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MSB EQU 0x00800000
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NORMAL EQU 0x00100000
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; Note: the SEH prolog below must match the SEH prolog for __addd.
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__subd
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STMFD sp!, {r0-r10, lr} ; Save off args and non-volatiles and lr
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MOV r8, r1 ; Load parameter1 as R8 R0
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MOV r4, r2 ; Load parameter2 as R2 R4
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MOV r2, r3 ; ...
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MOV r5, #_FpSubD ; Double add, assume no exceptions
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EOR r2, r2, #0x80000000
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; Toggle sign bit on parameter2
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B add_in ; Then go add
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; Note: the SEH prolog below must match the SEH prolog for __subd
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__addd
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STMFD sp!, {r0-r10, lr} ; Save off args and non-volatiles and lr
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MOV r8, r1 ; Load parameter1 as R8 R0
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MOV r4, r2 ; Load parameter2 as R2 R4
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MOV r2, r3 ; ...
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MOV r5, #_FpAddD ; Double add, assume no exceptions
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add_in
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; If abs(parameter1) < abs(parameter2) then swap them so that the resulting
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; parameter1 has the larger magnitude. This guarantees that only parameter2
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; might need to be shifted right before adding. Because of denormal numbers,
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; it's not sufficient to compare only the exponents; the entire mantissa must
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; be checked as well.
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;
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; if ((abs(parameter1).hi < abs(parameter1).hi) ||
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; ((abs(parameter1.hi == abs(parameter2)) &&
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; (parameter1.lo < parameter2.lo)))
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; swap parameter1 and parameter2
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MOV r3, r8, LSL #1 ; Extract copies of just the magnitudes
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CMP r3, r2, LSL #1 ; of each parameter
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CMPEQ r0, r4 ; if ((abs(param1).hi < abs(param2)).hi
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; ||
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BHS end_swap ; ((abs(param1).hi == abs(param2).hi)
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; &&
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; (param1.lo < param2.lo)))
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; ..
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swap
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MOV r3,r8 ; Swap parameter1 and parameter2
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MOV r8,r2 ; ..
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MOV r2,r3 ; ..
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MOV r3,r0 ; ..
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MOV r0,r4 ; ..
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MOV r4,r3 ; ..
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end_swap
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; Unpack parameters.
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;
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; R8 R0: mantissa1 R2 R4: mantissa2
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; R9: exponent1 R1: exponent2
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; R10: sign1 R6: sign2
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;
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; R5: Exception flags
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MOV r9, r8, LSL #1 ; Extract exponent1
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MOV r9, r9, LSR #21 ; ...
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MOV r1, r2, LSL #1 ; Extract exponent2
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MOV r1, r1, LSR #21 ; ...
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MVN r3, #0 ; Set up to extract mantissas
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MOV r10, r8 ; Extract sign1
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MOV r6, r2 ; Extract sign2
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AND r8, r8, r3, LSR #12; Extract mantissa1
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AND r2, r2, r3, LSR #12; Extract mantissa2
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; Check for exceptional cases. All NaNs, infinities, and 0's are eliminated.
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; Denormal numbers return here after normalizing them. After these checks,
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; both parameters are normalized numbers.
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;
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; After potentially swapping the parameters above, it's sufficient to test
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; just parameter1 for non-finite values (NaN, inf) to eliminate non-finite
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; values in either parameter. Similarly, it's sufficient to test just
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; parameter2 for the unnormalized numbers (exponent2 = 0; denormals and 0).
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;
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; if (exponent1 == 2047)
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; exception1; parameter1 is nonfinite, parameter2 might be too
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; if (exponent2 == 0)
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; exception2; parameter is 0 or denormal, parameter1 might be too
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ADD r3, r9, #1 ; if (exponent1==2047)
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CMP r3, #2048 ; ...
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BEQ exception1 ; exception1
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CMP r1, #0 ; if (exponent2==0)
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BEQ exception2 ; exception2
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exception_return2
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; Shift the mantissas left 3 bits to make room for guard, round and sticky bits
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; (G,R,S). Then set their hidden bits.
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MOV r8, r8, LSL #3 ; Shift mantissa1 left 3 for (G,R,S)
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ORR r8, r8, r0, LSR #29; ...
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MOV r0, r0, LSL #3 ; ...
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MOV r2, r2, LSL #3 ; Shift mantissa2 left 3 for (G,R,S)
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ORR r2, r2, r4, LSR #29; ...
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MOV r4, r4, LSL #3 ; ...
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ORR r8, r8, #0x00800000 ; Set each mantissa's hidden bit
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ORR r2, r2, #0x00800000 ; ..
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; Scale parameter2 so that its exponent matches that of parameter1, preparing
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; for the addition. Because of the swap earlier, parameter2 always scales by
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; shifting right (if it shifts at all).
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;
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; shift = exponent1 - exponent2
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; if shift <= -55
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; // entire mantissa2 shifts into the sticky bit; just set S
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; else
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; if (shift <= -32)
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; // "shift" by moving high word to low word
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; if (shift != 0)
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; // shift by dynamic shifting
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scale
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SUBS r1, r9, r1 ; shift = exponent2 - exponent1
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BEQ scale_end ; Shift == 0?
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CMP r1, #3 ;**;
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BLE scale_le_3 ;**; 0 < shift <= 3? ..
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CMP r1, #55 ; If shift <= 55 then
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BLE scale_le_55 ; ..
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MOV R2, #0 ; Else (mantissa2,G,R,S) = 1
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MOV R4, #1 ; ..
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B scale_end
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scale_le_3 ;**; No bits are ever lost
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MOV r4, r4, LSR r1 ; mantissa2 >>= x where 0 < x <= 3
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RSB r3, r1, #32
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ORR r4, r4, r2, LSL r3
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MOV r2, r2, LSR r1
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B scale_end
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scale_le_55 ; Else shift <= 55
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CMP r1, #31 ; If shift < 32
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BLE scale_le_31 ; ..
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CMP r4, #0 ; Else S = mantissa2.l != 0
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SUB r1, r1, #32 ; (32 fewer bits to shift)
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MOV r4, r2 ; Shift 32 bits by moving
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MOV r2, #0 ; ..
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ORRNE r4, r4, #1 ; Set S if shifted out bits
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scale_le_31
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CMP r1, #0 ; If shift != 0
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BEQ scale_end ; ..
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RSB r3, r1, #32 ; Get 32 - shift
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MOVS r7, r4, LSL r3 ; Extract low mantissa shifted out (Sticky==NE)
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MOV r7, r2, LSL r3 ; Extract high mantissa shifted into lower
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MOV r2, r2, LSR r1 ; Shift high mantissa into position
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MOV r4, r4, LSR r1 ; Shift low mantissa into position
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ORR r4, r4, r7 ; Insert bits from high mantissa into low
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ORRNE r4, r4, #1 ; Set sticky if shifted out bits
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scale_end
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; Add the mantissas.
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;
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; if (sign1 == sign2)
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; result = mantissa1 + mantissa2 // Same signs => addition
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; Scale result right if it carried
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; if (result overflowed)
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; return properly signed inf
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; else if (mantissa1 == mantissa2)
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; return +0 // Equal values => result = +0
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; else
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; result = mantissa1 - mantissa2 // Opposite signs => subtraction
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; Scale result left // High-order bits were lost
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EORS r7, r10, r6 ; If sign1 != sign2
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BMI mantissa_sub ; do subtract
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ADDS r0, r0, r4 ; Else result = mantissa1 + mantissa2
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ADC r8, r8, r2 ; ..
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CMP r8, #CARRY_CHECK; If the result carried
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BLT end_calc ; ..
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MOVS r8, r8, LSR #1 ; Then scale right one
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MOVS r0, r0, RRX ; ..
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ORRCS r0, r0, #1 ; (fold lost bit into S)
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ADD r9, r9, #1 ; Add 1 to exponent for shift
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ADD r3, r9, #1 ; Add 1 to exponent for compare
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CMP r3, #2048 ; EQ if overflow
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BLT end_calc ; ..
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; Overflowed so
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ORR r5, r5, #OVF_bit :OR: INX_bit
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; set exception flags
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MOV r0, #0 ; and return properly signed inf
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MOV r8, #0 ; ..
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B return_value ; ..
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; Return +0.
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plus_zero
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MOV r8, #0 ; Return +0
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MOV r0, #0 ; ..
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B return ; ..
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mantissa_sub
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CMP r8, r2 ; Else if mantissa1 = mantissa2
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CMPEQ r0, r4 ; ..
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BEQ plus_zero ; return +0
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man_sub1
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SUBS r0, r0, r4 ; Else result = mantissa1 - mantissa2
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SBC r8, r8, r2 ; ..
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;**; Parameter1 always has the larger magnitude; result is always its sign.
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; Normalize since high-order bits are lost when subtracting. Do this in
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; chunks.
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normalize
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CMP r8, #0 ; If mantissa.h = 0
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BNE norm32_end ; ..
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MOV r8, r0 ; mantissa <<= 32 by moving
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MOV r0, #0 ; ..
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SUB r9, r9, #32 ; exponent -= 32
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norm32_end
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MVN r3, #0 ; If (mantissa.h & 0xffff0000) = 0
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TST r8, r3, LSL #16 ; ..
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BNE norm16_end ;
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MOV r8, r8, LSL #16 ; mantissa <<= 16
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ORR r8, r8, r0, LSR #16
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MOV r0, r0, LSL #16
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SUB r9, r9, #16 ; exponent -= 16
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norm16_end
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CMP r8, #CARRY_CHECK ; If mantissa is not too far left
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BLO overnorm_end ; keep normalizing, otherwise, undo
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over_norm_loop
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MOVS r8, r8, LSR #1 ; mantissa1 >>= 1
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MOV r0, r0, RRX ; ..
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ADD r9, r9, #1 ; exponent1++
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CMP r8, #CARRY_CHECK ; If mantissa is still too far left
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BHS over_norm_loop ; ..
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B end_norm ; Done
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overnorm_end
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CMP r8, #MSB ; If mantissa is too far right
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BGE end_norm ; ..
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norm_loop
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MOVS r0, r0, LSL #1 ; mantissa1 <<= 1
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MOV r8, r8, LSL #1 ; ..
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ORRCS r8, r8, #1 ; ..
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SUB r9, r9, #1 ; exponent1--
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CMP r8, #MSB ; If mantissa is still too far right
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BLT norm_loop ; ..
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end_norm
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end_calc
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; Denormalize the result if necessary, with no concern for performance.
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; Addition (and thus subtraction) can never generate less significant bits than
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; those of the original operands. Thus, denormalization never results in lost
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; bits to fold into S.
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CMP r9, #0 ; If exponent < 0
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BGT end_denormal ; ..
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RSB r9, r9, #0 ; Then shift right exponent1 places
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ADD r9, r9, #1 ; +1 for the non-hidden bit
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denormal_loop
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MOVS r8, r8, LSR #1 ; ..
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MOV r0, r0, RRX ; ..
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SUBS r9, r9, #1 ; ..
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BNE denormal_loop ; ..
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end_denormal
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; Round to nearest. If rounding occurs, set inexact and
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; mantissa += G & ( L | R | S ). If the rounding carries, then renormalize.
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;
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; Addition (and thus subtraction) can never generate less significant bits than
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; those of the original operands. Thus, rounding can never meet either of the
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; IEEE loss of accuracy tests for underflow. Nor can rounding cause MaxDenorm
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; to carry to MinNormal.
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;
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; Test for inexact.
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TST r0, #0x7 ; If G|R|S (=> rounding required)
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BEQ end_round ; ..
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ORR r5, r5, #INX_bit; result is inexact (can't underflow)
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; Round to nearest.
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TST r0, #0x4 ; If G &&
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BEQ end_round ; ..
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TST r0, #0xB ; L|R|S
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|
|
BEQ end_round ; ..
|
||
|
|
ADDS r0, r0, #0x8 ; Then round the mantissa up
|
||
|
|
ADC r8, r8, #0 ;
|
||
|
|
|
||
|
|
CMP r8, #CARRY_CHECK; If the rounding carried
|
||
|
|
BLT end_round ; (mantissa >= 0x01000000)
|
||
|
|
ADD r9, r9, #2 ; Then renormalize
|
||
|
|
CMP r9, #2048 ; If rounding caused overflow
|
||
|
|
SUB r9, r9, #1
|
||
|
|
ORREQ r5, r5, #OVF_bit :OR: INX_bit
|
||
|
|
; Report overflow (=> inexact)
|
||
|
|
end_round
|
||
|
|
|
||
|
|
; Pack the result back into IEEE format.
|
||
|
|
|
||
|
|
return_value
|
||
|
|
MOV r0, r0, LSR #3 ; Shift mantissa right 3
|
||
|
|
ORR r0, r0, r8, LSL #29 ; ..
|
||
|
|
MOV r1, r8, LSR #3 ; ..
|
||
|
|
BIC r1, r1, #0x0FF00000
|
||
|
|
; Mask away the hidden bit and possibly one bit
|
||
|
|
; higher if round incremented mantissa.
|
||
|
|
; 0xFF<<20 is probably overkill, but safe.
|
||
|
|
ORR r1, r1, r9, LSL #20
|
||
|
|
; Merge exponent and mantissa
|
||
|
|
AND r10, r10, #0x80000000
|
||
|
|
ORR r1, r1, r10 ; Merge sign with exponent and mantissa
|
||
|
|
|
||
|
|
; If any trap enable flags are set corresponding to exception flags set,
|
||
|
|
; set the corresponding cause bits and cause a trap.
|
||
|
|
;
|
||
|
|
; if (exception)
|
||
|
|
; call handler
|
||
|
|
; extract the possibly updated result
|
||
|
|
; return
|
||
|
|
|
||
|
|
return
|
||
|
|
TST r5, #FPECause_mask ; If any exceptions occurred ...
|
||
|
|
BEQ done
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; Register usage:
|
||
|
|
;; r0 - Default result.low
|
||
|
|
;; r1 - Default result.high
|
||
|
|
;; r5 - Exception information
|
||
|
|
;;
|
||
|
|
;; Stack:
|
||
|
|
;; 0x10(sp) - up: Saved registers
|
||
|
|
;; 0xC(sp): Original Arg2.high
|
||
|
|
;; 0x8(sp): Original Arg2.low
|
||
|
|
;; 0x4(sp): Original Arg1.high
|
||
|
|
;; 0x0(sp): Original Arg1.low
|
||
|
|
;;
|
||
|
|
LDR r2, [sp, #0x8] ; Load original Arg2.low
|
||
|
|
LDR r3, [sp, #0xC] ; Load original Arg2.high
|
||
|
|
SUB sp, sp, #0x8 ; Make room for exception information
|
||
|
|
STR r2, [sp, #0x0] ; Store original Arg2.low
|
||
|
|
STR r3, [sp, #0x4] ; Store original Arg2.high
|
||
|
|
LDR r3, [sp, #0x8] ; Load original Arg1.low
|
||
|
|
LDR r2, [sp, #0xC] ; Load original Arg1.high
|
||
|
|
STR r0, [sp, #0x8] ; Store default result.low
|
||
|
|
STR r1, [sp, #0xC] ; Store default result.high
|
||
|
|
MOV r1, r5 ; Move exception information
|
||
|
|
ADD r0, sp, #0x10 ; Pointer for return value
|
||
|
|
|
||
|
|
;; Register Usage:
|
||
|
|
;; r0 - Address for return value = 0x10(sp)
|
||
|
|
;; r1 - Exception information
|
||
|
|
;; r2 - Original arg1.low
|
||
|
|
;; r3 - Original arg1.high
|
||
|
|
;;
|
||
|
|
;; Stack Usage:
|
||
|
|
;; 0x14(sp): Return result.high
|
||
|
|
;; 0x10(sp): Return result.low
|
||
|
|
;; 0xC(sp): Default result.high
|
||
|
|
;; 0x8(sp): Default result.low
|
||
|
|
;; 0x4(sp): Original arg2.high
|
||
|
|
;; 0x0(sp): Original arg2.low
|
||
|
|
|
||
|
|
CALL FPE_Raise ; Deal with exception information
|
||
|
|
|
||
|
|
IF Thumbing :LAND: :LNOT: Interworking
|
||
|
|
CODE16
|
||
|
|
bx pc ; switch back to ARM mode
|
||
|
|
nop
|
||
|
|
CODE32
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
LDR r0, [sp, #0x10] ; Load up returned result
|
||
|
|
LDR r1, [sp, #0x14] ; ...
|
||
|
|
ADD sp, sp, #0x8 ; Restore extra arg passing space
|
||
|
|
|
||
|
|
|
||
|
|
done
|
||
|
|
ADD sp, sp, #0x10 ; Pop off original args
|
||
|
|
IF Interworking :LOR: Thumbing
|
||
|
|
LDMIA sp!, {r4-r10, lr}
|
||
|
|
BX lr
|
||
|
|
ELSE
|
||
|
|
LDMIA sp!, {r4-r10, pc}
|
||
|
|
ENDIF
|
||
|
|
; Restore off non-volatiles and return
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
;%%%%%%%%%%%%%%%%%%%%%%%%%
|
||
|
|
;% Exceptional process %
|
||
|
|
;%%%%%%%%%%%%%%%%%%%%%%%%%
|
||
|
|
|
||
|
|
; Exception 1: parameter1 is non-finite (exponent1 == 2047). The mantissa has
|
||
|
|
; not been shifted left for the guard bits yet. The choice of ARM SNaN
|
||
|
|
; versus QNaN (mantissa<51> = 1 => QNaN) means that abs(<any QNaN>) >
|
||
|
|
; abs(<any SNaN>) > abs(<any inf>).
|
||
|
|
;
|
||
|
|
; exception1:
|
||
|
|
; if (mantissa1 == 0)
|
||
|
|
; CheckArg2INF(); // Arg1 is an INF. Must check Arg2 for INF.
|
||
|
|
; else if (mantissa1[MSb] == 0)
|
||
|
|
; SignalInvalid(); // Arg1 is an SNaN so signal invalid and return it.
|
||
|
|
; else
|
||
|
|
; CheckArg2SNaN(); // Arg1 is a QNaN. Check Arg2 for SNaN.
|
||
|
|
;
|
||
|
|
; CheckArg2SNaN:
|
||
|
|
; if (exponent2 == 2047 &&
|
||
|
|
; mantissa2 != 0 &&
|
||
|
|
; mantissa2[MSb] == 0)
|
||
|
|
; SignalInvalid();
|
||
|
|
; else
|
||
|
|
; ReturnQNaN();
|
||
|
|
;
|
||
|
|
; CheckArg2INF:
|
||
|
|
; if (exponent2 == 2047 &&
|
||
|
|
; mantissa2 == 0)
|
||
|
|
; if (sign1 ^ sign2)
|
||
|
|
; SignalInvalid(); // Arg1 and Arg2 are opposite INFs.
|
||
|
|
; else
|
||
|
|
; ReturnINF(); // Arg1 and Arg2 are same signed INFs.
|
||
|
|
; else
|
||
|
|
; ReturnINF(); // Arg1 is INF. Arg2 is not.
|
||
|
|
;
|
||
|
|
; SignalInvalid:
|
||
|
|
; cause |= INVALID_OPERATION;
|
||
|
|
; ReturnQNaN();
|
||
|
|
;
|
||
|
|
; ReturnQNaN:
|
||
|
|
; exponent1 = 2047;
|
||
|
|
; mantissa1[MSb] = 1;
|
||
|
|
; return();
|
||
|
|
;
|
||
|
|
; ReturnINF
|
||
|
|
; exponent1 = 2047;
|
||
|
|
; mantissa1 = 0;
|
||
|
|
; return();
|
||
|
|
;
|
||
|
|
exception1
|
||
|
|
ORRS r3, r8, r0 ; if (mantissa1 == 0)
|
||
|
|
BEQ CheckArg2INF ; CheckArg2INF
|
||
|
|
TST r8, #dSignalBit ; else if (mantissa1[MSb] == 0)
|
||
|
|
BEQ SignalInvalid ; SignalInvalid
|
||
|
|
; else
|
||
|
|
; CheckArg2SNaN
|
||
|
|
CheckArg2SNaN
|
||
|
|
ADD r3, r1, #1 ; if (exponent2 == 2047 &&
|
||
|
|
CMP r3, #2048 ; ..
|
||
|
|
BNE ReturnQNaN ; ..
|
||
|
|
ORRS r3, r2, r4 ; mantissa2 != 0 &&
|
||
|
|
BEQ ReturnQNaN ; ..
|
||
|
|
TST r2, #dSignalBit ; mantissa2[MSb] == 0)
|
||
|
|
BEQ SignalInvalid ; SignalInvalid
|
||
|
|
B ReturnQNaN ; else
|
||
|
|
; ReturnQNaN
|
||
|
|
CheckArg2INF
|
||
|
|
ADD r3, r1, #1 ; if (exponent2 == 2047 &&
|
||
|
|
CMP r3, #2048 ; ..
|
||
|
|
BNE ReturnINF ; ..
|
||
|
|
ORRS r3, r2, r4 ; mantissa2 == 0 &&
|
||
|
|
BNE ReturnINF ; ..
|
||
|
|
EORS r3, r10, r6 ; if (sign1 ^ sign2)
|
||
|
|
BMI SignalInvalid ; SignalInvalid
|
||
|
|
; else
|
||
|
|
; ReturnINF
|
||
|
|
|
||
|
|
ReturnINF
|
||
|
|
AND r1, r10, #0x80000000 ; Get sign bit
|
||
|
|
ORR r1, r1, r9, LSL #20 ; Insert exponent (exponent == 2047)
|
||
|
|
B return ; r0 is already 0 so just return
|
||
|
|
|
||
|
|
SignalInvalid
|
||
|
|
ORR r5, r5, #IVO_bit ; Set invalid operation
|
||
|
|
|
||
|
|
ReturnQNaN
|
||
|
|
AND r1, r10, #0x80000000 ; Get sign bit
|
||
|
|
ORR r1, r1, r9, LSL #20 ; Insert exponent (exponent == 2047)
|
||
|
|
ORR r1, r1, #dSignalBit ; Insert mantissa high bit to ensure QNaN
|
||
|
|
ORR r1, r1, r8 ; OR in rest of high mantissa bits
|
||
|
|
B return ; r0 already has the low mantissa bits so
|
||
|
|
; just return
|
||
|
|
|
||
|
|
|
||
|
|
; Exception 2: parameter1 is finite, parameter2 is not normal (0 or denormal).
|
||
|
|
;
|
||
|
|
; if (exponent1 == 0) // parameter1 is not normal
|
||
|
|
; if (mantissa1 == 0) // parameter1 is 0
|
||
|
|
; return properly signed 0
|
||
|
|
; else if (mantissa2 == 0) // denormal+denormal
|
||
|
|
; go normalize both and add
|
||
|
|
; else // denormal+0
|
||
|
|
; return parameter1
|
||
|
|
; else if (mantissa != 0) // parameter2 is denormal
|
||
|
|
; go normalize parameter2 and add
|
||
|
|
; else // parameter2 is 0
|
||
|
|
; return parameter1
|
||
|
|
|
||
|
|
exception2
|
||
|
|
CMP r9, #0 ; if parameter1 is not normal
|
||
|
|
BNE p1_normal ; ..
|
||
|
|
ORRS r7, r8, r0 ; if parameter1 is 0
|
||
|
|
BNE p1_denormal ; ..
|
||
|
|
;*** Rounding mode: proper sign is a function of the rounding mode.
|
||
|
|
AND r10, r10, r6 ; return properly signed 0
|
||
|
|
B return_value ;
|
||
|
|
|
||
|
|
p1_denormal
|
||
|
|
ORRS r7, r2, r4 ; else if parameter2 is denormal
|
||
|
|
BNE p1_normalize ; go normalize both and add
|
||
|
|
B return_p1 ; else parameter2 is 0
|
||
|
|
; return parameter1
|
||
|
|
p1_normal ; (parameter2 is denormal or 0)
|
||
|
|
ORRS r7, r2, r4 ; else if parameter2 is denormal
|
||
|
|
BNE p2_normalize ; go normalize parameter2 and add
|
||
|
|
return_p1 ; else parameter2 is 0
|
||
|
|
MOV r8, r8, LSL #3 ; return parameter1
|
||
|
|
ORR r8, r8, r0, LSR #29
|
||
|
|
; ..
|
||
|
|
MOV r0, r0, LSL #3 ; ..
|
||
|
|
B return_value ; ..
|
||
|
|
|
||
|
|
; Both parameter1 and parameter2 are denormal. Normalize both then go add.
|
||
|
|
|
||
|
|
p1_normalize ; Stop when we shift into 1.0 bit
|
||
|
|
MOVS r0, r0, LSL #1 ; Account for the hidden mantissa bit
|
||
|
|
MOV r8, r8, LSL #1 ; that denormals don't have
|
||
|
|
ORRCS r8, r8, #1 ; ..
|
||
|
|
CMP r8, #NORMAL ; While mantissa1 < 1.0
|
||
|
|
BGE end_p1_norm ; ..
|
||
|
|
p1_norm_loop
|
||
|
|
MOVS r0, r0, LSL #1 ; Scale mantissa1 up by 1 place
|
||
|
|
MOV r8, r8, LSL #1 ; ..
|
||
|
|
ORRCS r8, r8, #1 ; ..
|
||
|
|
SUB r9, r9, #1 ; and exponent1 down by 1
|
||
|
|
CMP r8, #NORMAL ; ..
|
||
|
|
BLT p1_norm_loop ; ..
|
||
|
|
end_p1_norm
|
||
|
|
|
||
|
|
; parameter1 is (now) normalized, parameter2 is denormal. Normalize
|
||
|
|
; parameter2 then go add.
|
||
|
|
|
||
|
|
p2_normalize ; Stop when we shift into 1.0 bit
|
||
|
|
MOVS r4, r4, LSL #1 ; Account for the hidden mantissa bit
|
||
|
|
MOV r2, r2, LSL #1 ; that denormals don't have
|
||
|
|
ORRCS r2, r2, #1 ; ..
|
||
|
|
CMP r2, #NORMAL ; While mantissa2 < 1.0
|
||
|
|
BGE end_p2_norm ; ..
|
||
|
|
p2_norm_loop
|
||
|
|
MOVS r4, r4, LSL #1 ; Scale mantissa2 up by 1 place
|
||
|
|
MOV r2, r2, LSL #1 ; ..
|
||
|
|
ORRCS r2, r2, #1 ; ..
|
||
|
|
SUB r1, r1, #1 ; and exponent2 down by 1
|
||
|
|
CMP r2, #NORMAL ; ..
|
||
|
|
BLT p2_norm_loop ; ..
|
||
|
|
end_p2_norm
|
||
|
|
B exception_return2
|
||
|
|
; Done
|
||
|
|
|
||
|
|
END
|