223 lines
8.9 KiB
NASM
223 lines
8.9 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; __i64tod: __int64 to double conversion routine.
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; __u64tod: unsigned __int64 to double conversion routine.
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;
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; Input: r1 - Most significant word of 64-bit integer to be converted
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; r0 - Least significant word of 64-bit integer to be converted
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;
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; Output: r1 - Most significant word of converted number to floating point
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; double precision format.
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; r0 - Least significant word of converted number to floating point
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; double precision format.
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; Local storage size and offsets
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LOC_SIZE EQU 0x18
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OrgOp1h EQU 0x14
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OrgOp1l EQU 0x10
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ExDResh EQU 0x0C
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ExDResl EQU 0x08
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NewResh EQU 0x14
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NewResl EQU 0x10
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GET fpe.asm
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GET kxarm.inc
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Export __u64tod
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Export __i64tod
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IMPORT FPE_Raise
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AREA |.text|, CODE, READONLY
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; Prolog must match __i64tod
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NESTED_ENTRY __u64tod
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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STR r0, [sp, #OrgOp1l] ; Save original arg in case of exception
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ORRS r2, r0, r1 ; Check for zero
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STR r1, [sp, #OrgOp1h] ; Save original arg in case of exception
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ADDEQ sp, sp, #LOC_SIZE ; If zero, restore stack and
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; return zero
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; return zero
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ENDIF
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MOV r14, #_FpU64ToD ; Initialize opcode, no exceptions
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MOV r12, #0 ; Initialize sign to 0 (positive)
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B LongSingleNormalize
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ENTRY_END __u64tod
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; Prolog must match __u64tod
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NESTED_ENTRY __i64tod
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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STR r0, [sp, #OrgOp1l] ; Save original arg in case of exception
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ORRS r2, r0, r1 ; Check for zero
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STR r1, [sp, #OrgOp1h] ; Save original arg in case of exception
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ADDEQ sp, sp, #LOC_SIZE ; If zero, restore stack and
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; return zero
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; return zero
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ENDIF
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MOV r14, #_FpI64ToD ; Initialize opcode, no exceptions
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ANDS r12, r1, #Sign_bit ; Extract sign
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BEQ LongSingleNormalize ; Positive value so do convert
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RSBS r0, r0, #0 ; Else we have a negative number so
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RSC r1, r1, #0 ; take the 2's complement inverse
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; Sign is in r12.
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; Mantissa abs(input 64-bit integer) is stored in r1:r0.
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;
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; Sign
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; +-+-------------------------------+
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; r12: |S|0000000000000000000000000000000|
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; +-+-------------------------------+
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;
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; Unnormalized mantissa
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; +--------------------------------+
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; r1: | Most Significant Word |
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; +--------------------------------+
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;
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; +--------------------------------+
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; r0: | Least Significant Word |
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; +--------------------------------+
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;
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; Only the high mantissa is shifted. After it is shifted into the correct
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; position, the low mantissa is shifted into place. The exception is the
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; first shift by 32 which moves the low mantissa into the high.
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;
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LongSingleNormalize
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MOV r2, #0 ; Exponent adjustment/mantissa shift
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CMP r1, #0 ; Any high 32 bits set?
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ADDEQ r2, r2, #32 ; If not, adjust exponent
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MOVEQ r1, r0 ; and shift the WHOLE mantissa
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MOVEQ r0, #0 ; ..
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MOVS r3, r1, LSR #16 ; Any high 16 bits set?
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ADDEQ r2, r2, #16 ; If not, adjust exponent
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MOVEQ r1, r1, LSL #16 ; and shift high mantissa
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TST r1, #0xFF000000 ; Any high 8 bits set?
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ADDEQ r2, r2, #8 ; If not, adjust exponent
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MOVEQ r1, r1, LSL #8 ; and shift high mantissa
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TST r1, #0xF0000000 ; Any high 4 bits set?
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ADDEQ r2, r2, #4 ; If not, adjust exponent
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MOVEQ r1, r1, LSL #4 ; and shift high mantissa
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TST r1, #0xC0000000 ; Any high 2 bits set?
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ADDEQ r2, r2, #2 ; If not, adjust exponent
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MOVEQS r1, r1, LSL #2 ; and shift high mantissa
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ADDPL r2, r2, #1 ; If high bit clear, adjust exponent
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MOVPL r1, r1, LSL #1 ; and shift high mantissa
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MOV r3, #DExp_bias+1 ; Load r3 = DExp_bias+63
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ADD r3, r3, #62 ; ..
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RSB r3, r2, r3 ; Calculate exponent
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ORR r12, r12, r3, LSL #DExp_pos
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; Combine sign and exponent
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CMP r2, #32 ; If all low shifted into high ...
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MOV r1, r1, LSL #1 ; Hide the hidden one
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ADD r2, r2, #1 ; ..
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BGE insert_mantissa ; ... just insert the mantissa
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; R2 contains the amount the mantissa has been shifted left, including
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; the shift for the hidden one. It is in the range 1..32. R1 contains
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; the high portion of the mantissa without any of R0 shifted into it.
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; R0 is unshifted. Note that the case where the entire low word was
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; shifted into the high word has already been taken care of and never
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; reaches this code.
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RSB r3, r2, #32 ; Determine amount of low mantissa
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; shifted into high mantissa
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ORR r1, r1, r0, LSR r3 ; Get part of low word shifted in high
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MOV r0, r0, LSL r2 ; Shift low word into position
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insert_mantissa
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ORR r3, r12, r1, LSR #12 ; Insert high word into result high
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MOV r2, r1, LSL #20 ; Insert high word into result low
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ORR r2, r2, r0, LSR #12 ; Insert low word into result low
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MOVS r0, r0, LSL #20 ; Check for inexact
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ORRNE r14, r14, #INX_bit ; Set inexact if bits are lost
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MOVS r0, r0, LSL #1 ; Round
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; CS -> guard bit
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; MI -> round bit
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; NE -> sticky bit | round bit
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BCC __i64tod_return ; If guard bit clear, leave result
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; Guard bit is set
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MOVS r0, r0, LSR #1 ; Must clear carry bit
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; NE -> sticky bit | round bit
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TSTEQ r2, #0x1 ; Check lost bit
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ADDNES r2, r2, #1 ; If G & (L | R | S) round up
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ADC r3, r3, #0 ; ..
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__i64tod_return
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MOV r1, r3 ; Move result into return regs
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MOV r0, r2 ; ..
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TST r14, #FPECause_mask ; Any exceptions?
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ADDEQ sp, sp, #LOC_SIZE ; pop off original arg, and
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; return
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; return
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ENDIF
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; Have an exception
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LDR r2, [sp, #OrgOp1l] ; Load original operand
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LDR r3, [sp, #OrgOp1h] ; ..
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STR r0, [sp, #ExDResl] ; Store default result
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STR r1, [sp, #ExDResh] ; ..
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ADD r0, sp, #NewResl ; Pointer to new result
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MOV r1, r14 ; Exception information
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CALL FPE_Raise ; Deal with exception information
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ; Load new result
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LDR r1, [sp, #NewResh] ; ..
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ADD sp, sp, #LOC_SIZE ; Pop off exception info and orig arg
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr} ; Return
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BX lr
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ELSE
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LDMFD sp!, {pc} ; Return
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ENDIF
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ENTRY_END __i64tod
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END
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