486 lines
19 KiB
C#
486 lines
19 KiB
C#
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////////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: Pic.cs
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//
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#define DEBUG_INTERRUPTS
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#define DEBUG_DISPATCH_IO
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#define PIC_DEBUG
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using Microsoft.Singularity.Io;
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using System;
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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using System.Threading;
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using Microsoft.Singularity.Configuration;
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using Microsoft.Singularity.Isal.Arm;
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namespace Microsoft.Singularity.Hal
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{
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// declare resources for the kernel manifest
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[DriverCategory]
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[Signature("/arm/ti/3430/INTCPS")]
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public sealed class PicResources : DriverCategoryDeclaration
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{
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[IoMemoryRange(0, Default = 0x48200000, Length = 0x1000)]
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internal readonly IoMemoryRange registers;
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// CTR will create the rest of this class:
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public PicResources(IoConfig config)
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{
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// dynamic resources
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registers = (IoMemoryRange)config.DynamicRanges[0];
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}
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}
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[CLSCompliant(false)]
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public sealed class Pic : HalPic
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{
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// size of register block
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const int PicRegisterSize = 0x00000280; // size of registers in block
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// registers
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const uint INTCPS_REVISION = 0x00000000; // INTCPS block revision
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const uint INTCPS_SYSCONFIG = 0x00000010; // configuration
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const uint INTCPS_SYSSTATUS = 0x00000014; // status
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const uint INTCPS_SIR_IRQ = 0x00000040; // IRQ source interrupt
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const uint INTCPS_SIR_FIQ = 0x00000044; // FIQ source interrupt
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const uint INTCPS_CONTROL = 0x00000048; // control
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const uint INTCPS_PROTECTION = 0x0000004c; // pic access control
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const uint INTCPS_IDLE = 0x00000050; // clock idling
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const uint INTCPS_IRQ_PRIORITY = 0x00000060; // IRQ priority level
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const uint INTCPS_FIQ_PRIORITY = 0x00000064; // FIQ priority level
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const uint INTCPS_THRESHHOLD = 0x00000068; // priority threshold control
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const uint INTCPS_ITR = 0x00000080; // raw interrupt status vector
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const uint INTCPS_MIR = 0x00000084; // interrupt mask vector
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const uint INTCPS_MIR_CLEAR = 0x00000088; // clear interrupt mask vector
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const uint INTCPS_MIR_SET = 0x0000008c; // set interrupt mask vector
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const uint INTCPS_ISR_SET = 0x00000090; // assert software interrupt vector
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const uint INTCPS_ISR_CLEAR = 0x00000094; // clear software interrupt vector
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const uint INTCPS_PENDING_IRQ = 0x00000098; // pending (masked) IRQ interrupt vector
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const uint INTCPS_PENDING_FIQ = 0x0000009c; // pending (masked) FIQ interrupt vector
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const uint INTCPS_ILR_Base = 0x00000100; // interrupt priority & fast/slow control
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const uint INTCPS_ILR_Offset = 0x00000004; // interrupt priority & fast/slow control
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// source interrupt fields
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const uint INTCPS_SIR_IRQ_ACTIVEIRQ_Mask = 0x0000007f; // active IRQ number
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const uint INTCPS_SIR_FIQ_ACTIVEFIQ_Mask = 0x0000007f; // active FIQ number
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// interrupt priority fields
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const uint INTCPS_IRQ_PRIORITY_Mask = 0x0000003f; // current irq priority
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const uint INTCPS_FIQ_PRIORITY_Mask = 0x0000003f; // current fiq priority
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// interrupt level/routing fields
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const uint INTCPS_ILR_FIQNIRQ = 0x00000001; // FIQ/IRQ routing
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const uint INTCPS_ILR_PRIORITY_Mask = 0x0000000d; // interrupt priority
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const int INTCPS_ILR_PRIORITY_Shift = 0x00000002; // interrupt priority
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// registers
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private IoMappedPort intcps_revision; // INTCPS block revision
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private IoMappedPort intcps_sysconfig; // configuration
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private IoMappedPort intcps_sysstatus; // status
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private IoMappedPort intcps_sir_irq; // IRQ source interrupt
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private IoMappedPort intcps_sir_fiq; // FIQ source interrupt
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private IoMappedPort intcps_control; // control
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private IoMappedPort intcps_protection; // pic access control
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private IoMappedPort intcps_idle; // clock idling
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private IoMappedPort intcps_irq_priority; // IRQ priority level
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private IoMappedPort intcps_fiq_priority; // FIQ priority level
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private IoMappedPort intcps_threshhold; // priority threshold control
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private IoMappedPort[] intcps_itr; // raw interrupt status vector
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private IoMappedPort[] intcps_mir; // interrupt mask vector
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private IoMappedPort[] intcps_mir_clear; // clear interrupt mask vector
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private IoMappedPort[] intcps_mir_set; // set interrupt mask vector
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private IoMappedPort[] intcps_isr_set; // assert software interrupt vector
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private IoMappedPort[] intcps_isr_clear; // clear software interrupt vector
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private IoMappedPort[] intcps_pending_irq; // pending (masked) IRQ interrupt vector
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private IoMappedPort[] intcps_pending_fiq; // pending (masked) FIQ interrupt vector
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private IoMappedPort intcps_ilr; // interrupt level/routing
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// constants for PIC interrupt vectors
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const byte INTCPS_Vectors = 0x60; // count of OMAP3430 interrupt vectors
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const byte INTCPS_Subvector_Size = 0x20; // size of sub-vectors
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private uint irqMask0; // copy of interrupt mask
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private uint irqMask1; // copy of interrupt mask
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private uint irqMask2; // copy of interrupt mask
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internal Pic(PnpConfig config)
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{
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PicResources pr = new PicResources(config);
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IoMemoryRange range = pr.registers;
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IoMemory regs = range.MemoryAtOffset(0, PicRegisterSize, Access.ReadWrite);
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intcps_revision = regs.MappedPortAtOffset(INTCPS_REVISION, 4, Access.Read);
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intcps_sysconfig = regs.MappedPortAtOffset(INTCPS_SYSCONFIG, 4, Access.ReadWrite);
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intcps_sysstatus = regs.MappedPortAtOffset(INTCPS_SYSSTATUS, 4, Access.Read);
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intcps_sir_irq = regs.MappedPortAtOffset(INTCPS_SIR_IRQ, 4, Access.Read);
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intcps_sir_fiq = regs.MappedPortAtOffset(INTCPS_SIR_FIQ, 4, Access.Read);
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intcps_control = regs.MappedPortAtOffset(INTCPS_CONTROL, 4, Access.ReadWrite);
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intcps_protection = regs.MappedPortAtOffset(INTCPS_PROTECTION, 4, Access.ReadWrite);
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intcps_idle = regs.MappedPortAtOffset(INTCPS_IDLE, 4, Access.ReadWrite);
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intcps_irq_priority = regs.MappedPortAtOffset(INTCPS_IRQ_PRIORITY, 4, Access.ReadWrite);
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intcps_fiq_priority = regs.MappedPortAtOffset(INTCPS_FIQ_PRIORITY, 4, Access.ReadWrite);
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intcps_threshhold = regs.MappedPortAtOffset(INTCPS_THRESHHOLD, 4, Access.ReadWrite);
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intcps_itr = CreatePortVector(regs, INTCPS_ITR, Access.Read);
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intcps_mir = CreatePortVector(regs, INTCPS_MIR, Access.ReadWrite);
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intcps_mir_clear = CreatePortVector(regs, INTCPS_MIR_CLEAR, Access.Write);
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intcps_mir_set = CreatePortVector(regs, INTCPS_MIR_SET, Access.Write);
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intcps_isr_set = CreatePortVector(regs, INTCPS_ISR_SET, Access.ReadWrite);
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intcps_isr_clear = CreatePortVector(regs, INTCPS_ISR_CLEAR, Access.Write);
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intcps_pending_irq = CreatePortVector(regs, INTCPS_PENDING_IRQ, Access.Read);
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intcps_pending_fiq = CreatePortVector(regs, INTCPS_PENDING_FIQ, Access.Read);
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intcps_ilr = regs.MappedPortAtOffset(
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INTCPS_ILR_Base,
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INTCPS_ILR_Offset * INTCPS_Vectors,
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Access.ReadWrite
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);
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}
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private static IoMappedPort[] CreatePortVector(IoMemory regs, uint offset, Access access)
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{
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return new IoMappedPort[3] {
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regs.MappedPortAtOffset(offset + 0x00, 4, access),
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regs.MappedPortAtOffset(offset + 0x20, 4, access),
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regs.MappedPortAtOffset(offset + 0x40, 4, access)
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};
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}
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public void Initialize()
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{
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DebugStub.WriteLine("Pic.Initializing IRQs");
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// mask all interrupts
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MaskAll();
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// clear all pending interrupts
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intcps_isr_clear[0].Write32(0xffffffff);
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intcps_isr_clear[1].Write32(0xffffffff);
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intcps_isr_clear[2].Write32(0xffffffff);
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}
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public void Finalize()
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{
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UnmaskAll();
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}
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[NoHeapAllocation]
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public override byte InterruptToIrq(byte interrupt)
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{
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DebugStub.WriteLine("Pic.InterruptToIrq({0})", __arglist(interrupt));
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// hack - all h/w interrupts on ARM are routed through a common vector
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DebugStub.Assert((interrupt == ExceptionVector.Fiq) ||
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(interrupt == ExceptionVector.Irq));
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IoResult result = IoResult.Success;
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if (interrupt == ExceptionVector.Fiq) {
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// read currently active FIQ
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ushort sir = intcps_sir_fiq.Read16NoThrow(ref result);
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return (byte)(sir & INTCPS_SIR_FIQ_ACTIVEFIQ_Mask);
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}
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else { // if (interrupt == ExceptionVector.Irq)
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// read currently active IRQ
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ushort sir = intcps_sir_irq.Read16NoThrow(ref result);
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return (byte)(sir & INTCPS_SIR_IRQ_ACTIVEIRQ_Mask);
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}
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}
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[NoHeapAllocation]
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public override byte IrqToInterrupt(byte irq)
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{
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DebugStub.WriteLine("Pic.IrqToInterrupt({0})", __arglist(irq));
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// range check
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DebugStub.Assert(irq < INTCPS_Vectors);
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// check where the interrupt is routed: IRQ or FIQ
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IoResult result = IoResult.Success;
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uint ilr = intcps_ilr.Read32NoThrow(irq * INTCPS_ILR_Offset, ref result);
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if ((ilr & INTCPS_ILR_FIQNIRQ) != 0) {
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return (byte)ExceptionVector.Fiq;
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}
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else {
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return (byte)ExceptionVector.Irq;
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}
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}
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public override byte MaximumIrq
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{
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[NoHeapAllocation]
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get { return INTCPS_Vectors - 1; }
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}
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[System.Diagnostics.Conditional("PIC_DEBUG")]
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[NoHeapAllocation]
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private void DumpBits(String label, IoMappedPort[] regs)
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{
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IoResult result = IoResult.Success;
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uint v0 = regs[0].Read32NoThrow(ref result);
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uint v1 = regs[1].Read32NoThrow(ref result);
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uint v2 = regs[2].Read32NoThrow(ref result);
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DebugStub.WriteLine(label, __arglist(v0, v1, v2));
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}
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[System.Diagnostics.Conditional("PIC_DEBUG")]
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[NoHeapAllocation]
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private void DumpRegisters()
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{
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IoResult result = IoResult.Success;
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ushort currentIrqNumber = (ushort)(intcps_sir_irq.Read16NoThrow(ref result)
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& INTCPS_SIR_IRQ_ACTIVEIRQ_Mask);
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ushort currentIrqPriority = (ushort)(intcps_irq_priority.Read16NoThrow(ref result)
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& (ushort)INTCPS_IRQ_PRIORITY_Mask);
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DebugStub.WriteLine("PIC Current IRQ: {0:x4} Priority: {0:x4}",
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__arglist(currentIrqNumber, currentIrqPriority));
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ushort currentFiqNumber = (ushort)(intcps_sir_fiq.Read16NoThrow(ref result)
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& INTCPS_SIR_FIQ_ACTIVEFIQ_Mask);
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ushort currentFiqPriority = (ushort)(intcps_fiq_priority.Read16NoThrow(ref result)
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& INTCPS_FIQ_PRIORITY_Mask);
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DebugStub.WriteLine("PIC Current FIQ: {0:x4} Priority: {0:x4}",
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__arglist(currentFiqNumber, currentFiqPriority));
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DumpBits("PIC raw interrupt status: {2:x8}{1:x8}{0:x8}", intcps_itr);
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DumpBits("PIC interrupt mask: {2:x8}{1:x8}{0:x8}", intcps_mir);
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DumpBits("PIC software interrupts: {2:x8}{1:x8}{0:x8}", intcps_isr_set);
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DumpBits("PIC pending IRQs: {2:x8}{1:x8}{0:x8}", intcps_pending_irq);
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DumpBits("PIC pending FIQs: {2:x8}{1:x8}{0:x8}", intcps_pending_fiq);
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for (uint i = 0; i < INTCPS_Vectors; ++i) {
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uint ilr = intcps_ilr.Read32NoThrow(i * INTCPS_ILR_Offset, ref result);
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string interruptType = ((ilr & INTCPS_ILR_FIQNIRQ) != 0) ? "fiq" : "irq";
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byte priority = (byte)((ilr & INTCPS_ILR_PRIORITY_Mask)
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>> INTCPS_ILR_PRIORITY_Shift);
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DebugStub.WriteLine("PIC ILR[{0}]: {1} Priority: {2:x2}",
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__arglist(i, interruptType, priority));
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}
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DebugStub.Assert(IoResult.Success == result);
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}
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[NoHeapAllocation]
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public override void ClearInterrupt(byte interrupt)
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{
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byte irq = InterruptToIrq(interrupt);
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Mask(irq);
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AckIrq(irq);
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Unmask(irq);
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#if DEBUG_INTERRUPTS
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DebugStub.WriteLine("pic.ClearInterrupt({2:x8}{1:x8}{0:x8})",
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__arglist(irqMask0, irqMask1, irqMask2));
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#endif
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}
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[NoHeapAllocation]
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public override void AckIrq(byte irq)
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{
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DebugStub.Assert(Processor.InterruptsDisabled());
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#if PIC_DEBUG
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DumpRegisters();
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#endif
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// Mark the IRQ as activated and mask it
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#if DEBUG_INTERRUPTS
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DebugStub.WriteLine("Int{0:x2} Acked, Mask={3:x8}{2:x8}{1:x8}",
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__arglist(irq, irqMask0, irqMask1, irqMask2));
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#endif
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// Quiet the interrupt controller.
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IoResult result = IoResult.Success;
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uint n = irq / 32u;
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uint bit = 1u << (irq % 32);
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if (n < intcps_isr_clear.Length) {
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intcps_isr_clear[n].Write32NoThrow(bit, ref result);
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}
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DebugStub.Assert(IoResult.Success == result);
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#if PIC_DEBUG
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DumpRegisters();
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#endif
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}
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[NoHeapAllocation]
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public override void EnableIrq(byte irq)
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{
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if (irq >= INTCPS_Vectors) {
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DebugStub.Break();
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// throw new OverflowException
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|
|
// (String.Format("irq {0} out of range.", irq));
|
||
|
|
}
|
||
|
|
|
||
|
|
#if DEBUG_INTERRUPTS
|
||
|
|
DebugStub.WriteLine("Int{0:x2} Enable, Mask={3:x8}{2:x8}{1:x8}",
|
||
|
|
__arglist(irq, irqMask0, irqMask1, irqMask2));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
bool saved = Processor.DisableInterrupts();
|
||
|
|
try {
|
||
|
|
Unmask(irq);
|
||
|
|
#if PIC_DEBUG
|
||
|
|
DumpRegisters();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
finally {
|
||
|
|
Processor.RestoreInterrupts(saved);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public override void DisableIrq(byte irq)
|
||
|
|
{
|
||
|
|
if (irq >= INTCPS_Vectors) {
|
||
|
|
DebugStub.Break();
|
||
|
|
// throw new OverflowException
|
||
|
|
// (String.Format("irq {0} out of range.", irq));
|
||
|
|
}
|
||
|
|
|
||
|
|
#if DEBUG_INTERRUPTS
|
||
|
|
DebugStub.WriteLine("Int{0:x2} Disable", __arglist(irq));
|
||
|
|
#endif
|
||
|
|
bool saved = Processor.DisableInterrupts();
|
||
|
|
try {
|
||
|
|
Mask(irq);
|
||
|
|
#if PIC_DEBUG
|
||
|
|
DumpRegisters();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
finally {
|
||
|
|
Processor.RestoreInterrupts(saved);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
//
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private void Mask(byte irq)
|
||
|
|
{
|
||
|
|
DebugStub.Assert(Processor.InterruptsDisabled());
|
||
|
|
uint n = irq / 32u;
|
||
|
|
uint bit = 1u << (irq % 32);
|
||
|
|
#if DEBUG_DISPATCH_IO
|
||
|
|
DebugStub.WriteLine("PIC.Mask({0}) => {1:x8}", __arglist(irq, bit));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
uint mask = GetMaskWord(n);
|
||
|
|
if ((mask & bit) == 0) {
|
||
|
|
|
||
|
|
#if DEBUG_DISPATCH_IO
|
||
|
|
DebugStub.WriteLine("-- Mask IRQs [{0}: old={1:x8} new={2:x8}",
|
||
|
|
__arglist(n, mask, mask | bit));
|
||
|
|
#endif
|
||
|
|
IoResult result = IoResult.Success;
|
||
|
|
intcps_mir_set[n].Write32NoThrow(bit, ref result);
|
||
|
|
DebugStub.Assert(IoResult.Success == result);
|
||
|
|
|
||
|
|
SetMaskWord(n, mask | bit);
|
||
|
|
#if PIC_DEBUG
|
||
|
|
DumpBits("-- PIC interrupt mask: {2:x8}{1:x8}{0:x8}", intcps_mir);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private void Unmask(byte irq)
|
||
|
|
{
|
||
|
|
DebugStub.Assert(Processor.InterruptsDisabled());
|
||
|
|
uint n = irq / 32u;
|
||
|
|
uint bit = 1u << (irq % 32);
|
||
|
|
#if DEBUG_DISPATCH_IO
|
||
|
|
DebugStub.WriteLine("PIC.Unmask({0}) => {1:x8}", __arglist(irq, bit));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
uint mask = GetMaskWord(n);
|
||
|
|
if ((mask & bit) != 0) {
|
||
|
|
|
||
|
|
#if DEBUG_DISPATCH_IO
|
||
|
|
DebugStub.WriteLine("-- Unmask IRQs [{0}: old={1:x8} new={2:x8}",
|
||
|
|
__arglist(n, mask, mask & ~bit));
|
||
|
|
#endif
|
||
|
|
#if false // Enable this to set interrupt without hardware.
|
||
|
|
IoResult result = IoResult.Success;
|
||
|
|
intcps_mir_clear[n].Write32NoThrow(bit, ref result);
|
||
|
|
intcps_isr_set[n].Write32NoThrow(bit, ref result);
|
||
|
|
DebugStub.Assert(IoResult.Success == result);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
SetMaskWord(n, mask & ~bit);
|
||
|
|
#if PIC_DEBUG
|
||
|
|
DumpBits("-- PIC interrupt mask: {2:x8}{1:x8}{0:x8}", intcps_mir);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public bool IrqMasked(byte irq)
|
||
|
|
{
|
||
|
|
uint n = irq / 32u;
|
||
|
|
uint bit = 1u << (irq % 32);
|
||
|
|
|
||
|
|
if (irq >= INTCPS_Vectors) {
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
return ((GetMaskWord(n) & bit) != 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private uint GetMaskWord(uint n)
|
||
|
|
{
|
||
|
|
switch (n) {
|
||
|
|
case 0: return irqMask0;
|
||
|
|
case 1: return irqMask1;
|
||
|
|
case 2: return irqMask2;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private void SetMaskWord(uint n, uint value)
|
||
|
|
{
|
||
|
|
switch (n) {
|
||
|
|
case 0: irqMask0 = value; break;
|
||
|
|
case 1: irqMask1 = value; break;
|
||
|
|
case 2: irqMask2 = value; break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private void MaskAll()
|
||
|
|
{
|
||
|
|
DebugStub.Assert(Processor.InterruptsDisabled());
|
||
|
|
|
||
|
|
for (int i = 0; i < intcps_mir_set.Length; i++) {
|
||
|
|
intcps_mir_set[i].Write32(0xffffffff);
|
||
|
|
}
|
||
|
|
irqMask0 = irqMask1 = irqMask2 = 0xffffffff;
|
||
|
|
}
|
||
|
|
|
||
|
|
private void UnmaskAll()
|
||
|
|
{
|
||
|
|
DebugStub.Assert(Processor.InterruptsDisabled());
|
||
|
|
|
||
|
|
for (int i = 0; i < intcps_mir_clear.Length; i++) {
|
||
|
|
intcps_mir_clear[i].Write32(0xffffffff);
|
||
|
|
}
|
||
|
|
irqMask0 = irqMask1 = irqMask2 = 0x0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|