329 lines
12 KiB
NASM
329 lines
12 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code handling dispatching of interrupts.
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CODE32
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AREA |.text|, CODE, ARM, ALIGN=5
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|defining ?g_LoadResetVector@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ| EQU 1
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|defining ?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ| EQU 1
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|defining ?g_SetModeSp@Class_Microsoft_Singularity_Isal_Isa@@SAXHPAUuintPtr@@@Z| EQU 1
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INCLUDE hal.inc
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;;; These are exported so we can see, in the debugger, which exception was triggered.
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EXPORT |DispatchReset|
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EXPORT |DispatchUndefinedInstruction|
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EXPORT |DispatchSupervisorCall|
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EXPORT |DispatchPrefetchAbort|
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EXPORT |DispatchDataAbort|
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EXPORT |DispatchUnused|
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EXPORT |DispatchIrq|
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EXPORT |DispatchFiq|
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EXPORT |VectorReset|
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EXPORT |VectorUndefinedInstruction|
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EXPORT |VectorSupervisorCall|
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EXPORT |VectorPrefetchAbort|
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EXPORT |VectorDataAbort|
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EXPORT |VectorUnused|
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EXPORT |VectorIrq|
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EXPORT |VectorFiq|
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;;;
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;;; "public: static void __cdecl Class_Microsoft_Singularity_Isal_Isa::g_LoadIdt(void)"
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;;; Loads the address of the exception vectors into the VBAR.
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;;;
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LEAF_ENTRY ?g_LoadResetVector@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ
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;; Load the address of the 0 interrupt vector into r0.
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adr r0, VectorReset
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;; Load R0 into VBAR. Note: This code is ARMv7 specific.
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mcr p15,0,r0,c12,c0,0
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bx lr
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LEAF_END
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;;; SetModeSp sets the stack pointer in the target mode to the value passed in.
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LEAF_ENTRY ?g_SetModeSp@Class_Microsoft_Singularity_Isal_Isa@@SAXHPAUuintPtr@@@Z
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;; r0 arg contains the target mode
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;; r1 arg contains the value for sp
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mrs r2, cpsr
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bic r3, r2, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Mask
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orr r3, r3, r0
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msr cpsr_c, r3
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mov sp, r1
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msr cpsr_c, r2
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bx lr
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LEAF_END
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LTORG
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;;; VectorX indicates a branch instruction in the exception vector
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;;; Note that these 8 1-instruction functions must be laid out in exactly
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;;; this order as this *IS* the hardware exception vector on ARM.
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LEAF_ENTRY VectorReset
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ldr pc, [pc, #24] ; b |DispatchReset|
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LEAF_END
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LEAF_ENTRY VectorUndefinedInstruction
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ldr pc, [pc, #24] ;b |DispatchUndefinedInstruction|
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LEAF_END
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LEAF_ENTRY VectorSupervisorCall
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ldr pc, [pc, #24] ;b |DispatchSupervisorCall|
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LEAF_END
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LEAF_ENTRY VectorPrefetchAbort
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ldr pc, [pc, #24] ;b |DispatchPrefetchAbort|
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LEAF_END
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LEAF_ENTRY VectorDataAbort
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ldr pc, [pc, #24] ;b |DispatchDataAbort|
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LEAF_END
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LEAF_ENTRY VectorUnused
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ldr pc, [pc, #24] ;b |DispatchUnused|
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LEAF_END
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LEAF_ENTRY VectorIrq
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ldr pc, [pc, #24] ;b |DispatchIrq|
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LEAF_END
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LEAF_ENTRY VectorFiq
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ldr pc, [pc, #24] ;b |DispatchFiq|
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LEAF_END
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BeginRedirections
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DCD |DispatchReset|
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DCD |DispatchUndefinedInstruction|
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DCD |DispatchSupervisorCall|
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DCD |DispatchPrefetchAbort|
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DCD |DispatchDataAbort|
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DCD |DispatchUnused|
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DCD |DispatchIrq|
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DCD |DispatchFiq|
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EndOfRedirections
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;;; Interrupt dispatching on ARM occurs at fixed memory locations (either 0-based or
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;;; FFFF0000-based). For now we use the zero base exclusively.
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;;; ARM has 7 interrupt categories. Currently we use a simplified model, which
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;;; matches other architectures (i.e. we move to a single per-processor interrupt
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;;; stack for all interrupt handling.)
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;;;
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;;; Modes:
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;;; IRQ: this is normal device interrupt we expect to get.
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;;; Abort: both types of aborts correspond to normal software exceptions,
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;;; (which are currently just forwarded to the debugger)
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;;; All other interrupts are assumed to be anomalous, and are also passed to the debugger.
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;;; FIQ: we don't want to write special interrupt handlers currently, so this
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;;; mode has no benefit
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;;; SWI, Reset: no cases of these yet.
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;;;
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;;; We do not execute substantial amounts of code in IRQ mode. This is because
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;;; a nested IRQ interrupt would trash our lr register. (We don't take nested IRQ's
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;;; now, but likely will eventually.)
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;;; The GO_DISPATCH macro creates an InterruptContext at the top of the interrupted
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;;; stack and save R0-R3 and the exception vector number into it (takes as an argument).
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;;; GO_DISPATCH branches to |GoDispatchPhase2| which saves the rest of the caller-saved
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;;; registers and switches to system mode. If $save is true, the faulting instruction
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;;; opcode is saved as well.
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;;; Note that this code requires the interrupt mode sp to point to a DispatchStack structure.
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MACRO
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GO_DISPATCH $vector, $save
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;; Sp in interrupt mode will always point at a per-cpu DispatchStack structure
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;; Free R4 and fetch interrupted SP.
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stmia sp, {r4,sp}^ ; Stored to Struct_Microsoft_Isal_Arm_DispatchStack
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;; Load address of interrupt context from interrupted SP.
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ldr r4, [sp, #Struct_Microsoft_Singularity_Isal_Arm_DispatchStack___sp]
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sub r4, r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___SIZE
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;; Save the unbanked user volatile regs (this gets us some scratch regs)
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stmia r4, {r0-r3,r12}
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;; Save vector
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ldr r0, =$vector
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str r0, [r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___vector]
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;; Save interrupted PC.
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sub r0, lr, #4
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str r0, [r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___pc]
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;; Save faulting instruction (from the pc in r0)
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IF $save
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ldr r0, [r0]
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ELSE
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ldr r0, =0
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ENDIF
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str r0, [r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___instruction]
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;; Continue in share code (with r4 == InterruptContext)
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b |GoModePhase2|
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MEND
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;;;
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|GoModePhase2| PROC
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;; Save the banked interrupted registers (use R3 as pointer to banked registers).
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add r3, r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___sp
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stmia r3, {sp,lr}^
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;; Save interrupted CPSR.
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mrs r0, spsr
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str r0, [r4, #Struct_Microsoft_Singularity_Isal_InterruptContext___cpsr]
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;; Move InterruptContext pointer to r3 and restore r4 from DispatchStack.
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mov r3, r4
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ldr r4, [sp, #Struct_Microsoft_Singularity_Isal_Arm_DispatchStack___r4]
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;; Switch to system mode
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mrs r0, cpsr
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bic r0, r0, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Mask
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orr r0, r0, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_System
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msr cpsr_c, r0
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;; Restore SP to top of the InterruptContext (i.e. old sp - sizeof(InterruptContext)).
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mov sp, r3
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;; Jump to common dispatch routine. (with r3 = InterruptContext)
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b |?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ|
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ENDP
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;;; DispatchX is the dispatch routine for vector X. This code is largely identical
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;;; for all the vectors, except for the ID constant which is pushed in the frame
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;;; TBD: sharing more code would be a good thing, but it's tough to find a place to stash
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;;; the interrupt id.
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LEAF_ENTRY DispatchReset
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_Reset,{false}
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LEAF_END
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LEAF_ENTRY DispatchUndefinedInstruction
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_UndefinedInstruction,{true}
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LEAF_END
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LEAF_ENTRY DispatchSupervisorCall
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_SoftwareInterrupt,{true}
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LEAF_END
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LEAF_ENTRY DispatchPrefetchAbort
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_PrefetchAbort,{false}
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LEAF_END
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LEAF_ENTRY DispatchDataAbort
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_DataAbort,{true}
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LEAF_END
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LEAF_ENTRY DispatchUnused
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_Unused,{false}
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LEAF_END
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LEAF_ENTRY DispatchIrq
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_Irq,{false}
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LEAF_END
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LEAF_ENTRY DispatchFiq
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GO_DISPATCH Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_Fiq,{false}
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LEAF_END
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|DispatchTableEnd|
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;;; DispatchVector implements the meat of the low level interrupt dispatching logic. Its goal
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;;; is to implement the transition to high level code with minimal overhead.
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|?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ| PROC
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;; Pick the correct spill context based on the interrupt vector.
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;; Our normal scheduler-capable interrupts are IRQ's. Other exceptions
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;; are just reported to the debugger for now.
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;;
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;; TODO: Note that we are not implementing a "no scheduler switch" category
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;; of interrupts for now, so we won't be able to handle nested interrupts. This will
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;; be easy to change if we can figure out the right criteria to identify such interrupts
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;; at this level later on.
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;;
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;;
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ldr r0, [sp, #Struct_Microsoft_Singularity_Isal_InterruptContext___vector]
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cmp r0, #Struct_Microsoft_Singularity_Isal_Arm_ExceptionVector_Irq
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bne |debug|
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;; Use current thread's spill context
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GET_THREAD_FIELD_ADDR r0, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___spill
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b |save|
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|debug| ;; Use cpu's spill context
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GET_CPU_FIELD_ADDR r0, r12, #Struct_Microsoft_Singularity_Isal_CpuRecord___spill
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|save| ;; Save to spill context
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mov r1, sp
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bl |?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SA_NPAU1@PAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z|
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;; Save previous stack limit
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GET_THREAD_FIELD_ADDR r0, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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ldr r0, [r0]
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PUSH r0
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;; See if we are already on the interrupt stack
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GET_CPU_FIELD_ADDR r1, r12, #Struct_Microsoft_Singularity_Isal_CpuRecord___interruptStackLimit
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ldr r1, [r1]
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cmp r1, r0
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;; Stash current sp
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mov r0, sp
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beq |no_switch|
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;; Now switch to the interrupt stack
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GET_CPU_FIELD_ADDR r2, r12, #Struct_Microsoft_Singularity_Isal_CpuRecord___interruptStackBegin
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ldr sp, [r2]
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GET_THREAD_FIELD_ADDR r2, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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str r1, [r2]
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|no_switch|
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;; Save the old stack pointer
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PUSH r0
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;; Interrupt context is old stack pointer + 4
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add r0, r0, #4
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;; Call dispatch routine
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bl |?g_DispatchInterrupt@Class_Microsoft_Singularity_Isal_Isa@@SAXPAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z|
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;; Restore the old stack pointer and limit
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POP sp
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POP r0
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GET_THREAD_FIELD_ADDR r1, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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str r0, [r1]
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;; Now we need to switch back to interrupt mode so we can do a proper atomic resume (using spsr)
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mov r1, sp
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mrs r0, cpsr
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bic r0, r0, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Mask
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orr r0, r0, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Supervisor
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msr cpsr_c, r0
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;; Move saved CPSR into SPSR
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ldr r0, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___cpsr]
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msr spsr, r0
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;; Restore banked pre-interrupt registers (use R3 as pointer to banked registers).
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add r3, r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___sp
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ldmia r3, {sp,lr}^
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;; Resume unbanked pre-interrupt state
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ldmfd r1, {r0-r3,r12,pc}^
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ENDP
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END
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