440 lines
18 KiB
Plaintext
440 lines
18 KiB
Plaintext
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///////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: Perfcnt.cs
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//
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using Microsoft.Singularity.Processor;
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using System;
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using System.Runtime.CompilerServices;
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using System.Globalization;
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using System.Threading;
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using Microsoft.Singularity.Channels;
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using Microsoft.Contracts;
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using Microsoft.SingSharp.Reflection;
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using Microsoft.Singularity.Applications;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Configuration;
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[assembly: Transform(typeof(ApplicationResourceTransform))]
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namespace Microsoft.Singularity.Applications
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{
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[ConsoleCategory(HelpMessage="HW performance counter utility", DefaultAction=true)]
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internal class Parameters
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{
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[InputEndpoint("data")]
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public readonly TRef<UnicodePipeContract.Exp:READY> Stdin;
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[OutputEndpoint("data")]
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public readonly TRef<UnicodePipeContract.Imp:READY> Stdout;
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[BoolParameter( "k", Default=false, HelpMessage="Configure for kompute-bound counting.")]
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internal bool doComputeBound;
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[BoolParameter( "g", Default=false, HelpMessage="Configure for general counting.")]
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internal bool doGeneral;
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[BoolParameter( "i", Default=false, HelpMessage="Configure for I/O counting.")]
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internal bool doIO;
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[BoolParameter( "t", Default=false, HelpMessage="Configure for TLB counting.")]
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internal bool doTLB;
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[BoolParameter( "d", Default=false, HelpMessage="Configure for Data Cache counting.")]
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internal bool doCache;
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[BoolParameter( ".", Default=false, HelpMessage="Simple test.")]
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internal bool doDot;
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[BoolParameter( ",", Default=false, HelpMessage="Simple test.")]
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internal bool doComma;
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[BoolParameter( "z", Default=false, HelpMessage="Simple test.")]
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internal bool doZ;
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[BoolParameter( "s", Default=false, HelpMessage="Show counters.")]
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internal bool doShow;
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[BoolParameter( "b", Default=false, HelpMessage="Configure for branch counting.")]
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internal bool doBranch;
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[LongParameter( "e", Default=-1, HelpMessage="Configure performance counter 'n'.")]
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internal long eventCounter;
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[LongParameter( "ev", Default=-1, HelpMessage="Configure event value 'v'.")]
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internal long eventValue;
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[LongParameter( "p", Default=-1, HelpMessage="Read performance counter 'n'.")]
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internal long counterReg;
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[LongParameter( "c", Default=-1, HelpMessage="Read CPUID function 'n'.")]
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internal long cpuidReg;
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[LongParameter( "w", Default=-1, HelpMessage="Write 'v' to MSR 'n'.")]
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internal long writeReg;
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[LongParameter( "wv", Default=-1, HelpMessage="Write 'v' to MSR 'n'.")]
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internal long writeValue;
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[LongParameter( "r", Default=-1, HelpMessage="Read MSR 'n'.")]
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internal long msrReg;
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reflective internal Parameters();
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internal int AppMain() {
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return Perfcnt.AppMain(this);
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}
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}
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[CLSCompliant(false)]
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public struct PerfEvtSel
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{
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// Bits and Flags
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public const uint CNT_MASK = 0xff000000;
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public const uint INV = 0x00800000;
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public const uint EN = 0x00400000;
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public const uint INT = 0x00100000;
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public const uint PC = 0x00080000;
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public const uint E = 0x00040000;
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public const uint OS = 0x00020000;
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public const uint USR = 0x00010000;
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public const uint UNIT_MASK = 0x0000ff00;
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public const uint SELECTOR = 0x000000ff;
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// Common setting: Count all, but don't interrupt,
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public const uint COUNT = (EN | PC | OS | USR);
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// public const uint COUNT = (EN | PC | E | OS | USR);
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// Selector values.
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public const uint DCacheRefillFromL2OrSys = 0x42; // Speculative
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public const uint DCacheRefillFromSystem = 0x43; // Speculative
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public const uint DtlbL1MissL2Hit = 0x45; // Speculative
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public const uint DtlbL1MissL2Miss = 0x46; // Speculative
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public const uint CyclesNotHalted = 0x76; // No E
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public const uint RequestsToL2Cache = 0x7d;
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public const uint L2CacheMiss = 0x7e;
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public const uint ItlbL1MissL2Hit = 0x84;
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public const uint ItlbL1MissL2Miss = 0x85;
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public const uint RetiredInstructions = 0xc0; // No E
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public const uint RetiredBranchInstructions = 0xc2; // No E
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public const uint RetiredBranchesMispredicted = 0xc3; // No E
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public const uint RetiredBranchesTaken = 0xc4; // No E
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public const uint CyclesInterruptsMasked = 0xcd; // No E
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public const uint CyclesInterruptsBlocked = 0xce; // No E
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}
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public class Perfcnt
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{
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public static bool IsIntel;
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public static bool IsAmd;
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public static ulong Parse(string! value)
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{
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if (value.StartsWith("0x") || value.StartsWith("0X")) {
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return System.UInt64.Parse(value, NumberStyles.AllowHexSpecifier);
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}
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else {
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return System.UInt64.Parse(value);
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}
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}
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public static void Reset(uint pmc, ulong value)
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{
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if (IsAmd) {
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// Clear the event selector.
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Processor.WriteMsr(0xc0010000 + pmc, 0);
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// Clear the performance counter.
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Processor.WriteMsr(0xc0010004 + pmc, 0);
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// Enable the event selector.
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Processor.WriteMsr(0xc0010000 + pmc, value);
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}
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}
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public static void ResetGlobalPerfCounters()
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{
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DebugStub.WritePerfCounter(0, 0);
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DebugStub.WritePerfCounter(1, 0);
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DebugStub.WritePerfCounter(2, 0);
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DebugStub.WritePerfCounter(3, 0);
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}
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public static void Clear()
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{
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Console.WriteLine("Clearing counters to zero.");
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ResetGlobalPerfCounters();
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if (IsAmd) {
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for (uint pmc = 0; pmc < 4; pmc++) {
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Processor.WriteMsr(0xc0010004 + pmc, 0);
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}
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}
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
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}
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public static string EvtSelToString(ulong value)
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{
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switch (value & 0xff) {
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case PerfEvtSel.DCacheRefillFromL2OrSys: return "DCache_Refill_L2";
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case PerfEvtSel.DCacheRefillFromSystem: return "DCache_Refill_Sys";
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case PerfEvtSel.DtlbL1MissL2Hit: return "DTLB_L2_Hit";
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case PerfEvtSel.DtlbL1MissL2Miss: return "DTBL_L2_Miss";
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case PerfEvtSel.CyclesNotHalted: return "CyclesNotHalted";
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case PerfEvtSel.RequestsToL2Cache:
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if ((value & 0x400) != 0) {
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return "TLB_L2_Requests";
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}
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return "Req_L2_Cache";
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case PerfEvtSel.L2CacheMiss:
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if ((value & 0x400) != 0) {
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return "TLB_L2_Miss";
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}
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return "L2_Cache_Miss";
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case PerfEvtSel.ItlbL1MissL2Hit: return "ITLB_L2_Hit";
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case PerfEvtSel.ItlbL1MissL2Miss: return "ITLB_L2_Miss";
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case PerfEvtSel.RetiredInstructions: return "Retired_Inst.";
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case PerfEvtSel.RetiredBranchInstructions: return "Branches";
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case PerfEvtSel.RetiredBranchesMispredicted:return "Br_Mispredicted";
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case PerfEvtSel.RetiredBranchesTaken: return "Br_Taken";
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case PerfEvtSel.CyclesInterruptsMasked: return "Ints_Masked (cyc)";
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case PerfEvtSel.CyclesInterruptsBlocked: return "Ints_Blocked (cyc)";
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default:
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return String.Format("{0:x16}", value);
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}
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}
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public static void DumpNow(bool config)
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{
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ulong b0 = DebugStub.ReadPerfCounter(7);
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ulong t0 = Processor.GetCycleCount();
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ulong e0 = Processor.ReadMsr(0xc0010000);
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ulong e1 = Processor.ReadMsr(0xc0010001);
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ulong e2 = Processor.ReadMsr(0xc0010002);
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ulong e3 = Processor.ReadMsr(0xc0010003);
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ulong p0 = Processor.ReadPmc(0);
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ulong p1 = Processor.ReadPmc(1);
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ulong p2 = Processor.ReadPmc(2);
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ulong p3 = Processor.ReadPmc(3);
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ulong z0 = DebugStub.ReadPerfCounter(0);
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ulong z1 = DebugStub.ReadPerfCounter(1);
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ulong z2 = DebugStub.ReadPerfCounter(2);
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ulong z3 = DebugStub.ReadPerfCounter(3);
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t0 = t0 - b0;
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if (config) {
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Console.WriteLine("evt: {0:x16} {1:x16} {2:x16} {3:x16}", e0, e1, e2, e3);
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}
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Console.WriteLine("evt: {0,16} {1,16} {2,16} {3,16}",
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EvtSelToString(e0),
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EvtSelToString(e1),
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EvtSelToString(e2),
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EvtSelToString(e3));
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Console.WriteLine("pmc: {0:d16} {1:d16} {2:d16} {3:d16}",
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p0, p1, p2, p3);
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Console.WriteLine("pfc: {0:d16} {1:d16} {2:d16} {3:d16}",
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z0, z1, z2, z3);
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DebugStub.WriteLine("evt: {0,16} {1,16} {2,16} {3,16} {4,16}",
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__arglist("Cycles",
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EvtSelToString(e0),
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EvtSelToString(e1),
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EvtSelToString(e2),
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EvtSelToString(e3)));
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DebugStub.WriteLine("pmc: {0:d16} {1:d16} {2:d16} {3:d16} {4:d16}",
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__arglist(t0, p0, p1, p2, p3));
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DebugStub.WriteLine("pfc: {0:d16} {1:d16} {2:d16} {3:d16} {4:d16}",
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__arglist(z0 + z1 + z2 + z3, z0, z1, z2, z3));
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}
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internal static int AppMain(Parameters! config)
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{
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// Temporaries for command-line parsing
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uint eax;
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uint ebx;
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uint ecx;
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uint edx;
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Processor.ReadCpuid(0, out eax, out ebx, out ecx, out edx);
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) {
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IsIntel = true;
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}
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) {
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IsAmd = true;
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}
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uint reg;
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ulong val;
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if (config.eventCounter != -1) { // program event selector N.
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reg = (uint) config.eventCounter;
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val = (ulong) config.eventValue;
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if (config.eventValue == -1) {
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Console.WriteLine("Must specify both -en and -ev to configure an event.");
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return -1;
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}
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Reset(reg, val);
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Console.WriteLine("Reset pmc{0}:{1:x16}", reg, val);
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}
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if (config.counterReg != -1) { // read performance counter.
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reg = (uint)config.counterReg;
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val = Processor.ReadPmc(reg);
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Console.WriteLine("read pmc{0}:{1:x16}", reg, val);
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}
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if (config.doBranch) { // configure for branch evaluation.
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ResetGlobalPerfCounters();
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Reset(0, PerfEvtSel.COUNT | PerfEvtSel.RetiredInstructions);
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Reset(1, PerfEvtSel.COUNT | PerfEvtSel.RetiredBranchInstructions);
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Reset(2, PerfEvtSel.COUNT | PerfEvtSel.RetiredBranchesMispredicted);
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Reset(3, PerfEvtSel.COUNT | PerfEvtSel.RetiredBranchesTaken);
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
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}
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if (config.doComputeBound) { // configure for compute-bound tasks.
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ResetGlobalPerfCounters();
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Reset(0, PerfEvtSel.COUNT | PerfEvtSel.RetiredInstructions);
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Reset(1, PerfEvtSel.COUNT | PerfEvtSel.RetiredBranchInstructions);
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Reset(2, PerfEvtSel.COUNT | PerfEvtSel.RequestsToL2Cache | 0x400);
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Reset(3, PerfEvtSel.COUNT | PerfEvtSel.L2CacheMiss | 0x300);
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
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}
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if (config.doGeneral) { // configure for General evaluation.
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ResetGlobalPerfCounters();
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Reset(0, PerfEvtSel.COUNT | PerfEvtSel.CyclesNotHalted);
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Reset(1, PerfEvtSel.COUNT | PerfEvtSel.RetiredInstructions);
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Reset(2, PerfEvtSel.COUNT | PerfEvtSel.CyclesInterruptsMasked);
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Reset(3, PerfEvtSel.COUNT | PerfEvtSel.RequestsToL2Cache | 0x400);
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
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}
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if (config.doIO) { // configure for I/O counting.
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ResetGlobalPerfCounters();
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Reset(0, PerfEvtSel.COUNT | PerfEvtSel.CyclesNotHalted);
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Reset(1, PerfEvtSel.COUNT | PerfEvtSel.RetiredInstructions);
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Reset(2, PerfEvtSel.COUNT | PerfEvtSel.CyclesInterruptsMasked);
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Reset(3, PerfEvtSel.COUNT | PerfEvtSel.CyclesInterruptsBlocked);
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
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}
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if (config.doTLB) { // configure for TLB counting.
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// Just count TLB page walks on L2 Cache.
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ResetGlobalPerfCounters();
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Reset(0, PerfEvtSel.COUNT | PerfEvtSel.RequestsToL2Cache | 0x400);
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Reset(1, PerfEvtSel.COUNT | PerfEvtSel.L2CacheMiss | 0x400);
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Reset(2, PerfEvtSel.COUNT | PerfEvtSel.DtlbL1MissL2Hit);
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Reset(3, PerfEvtSel.COUNT | PerfEvtSel.DtlbL1MissL2Miss);
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DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.doCache) { // Data Cache
|
||
|
|
// Just count TLB page walks on L2 Cache.
|
||
|
|
ResetGlobalPerfCounters();
|
||
|
|
Reset(0, PerfEvtSel.COUNT | PerfEvtSel.RequestsToL2Cache | 0x300);
|
||
|
|
Reset(1, PerfEvtSel.COUNT | PerfEvtSel.L2CacheMiss | 0x300);
|
||
|
|
Reset(2, PerfEvtSel.COUNT | PerfEvtSel.DCacheRefillFromSystem | 0x1f00);
|
||
|
|
Reset(3, PerfEvtSel.COUNT | PerfEvtSel.DCacheRefillFromL2OrSys);
|
||
|
|
DebugStub.WritePerfCounter(7, Processor.GetCycleCount());
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.cpuidReg != -1) { // read cpuid.
|
||
|
|
reg = (uint)config.cpuidReg;
|
||
|
|
uint v0;
|
||
|
|
uint v1;
|
||
|
|
uint v2;
|
||
|
|
uint v3;
|
||
|
|
Processor.ReadCpuid(reg, out v0, out v1, out v2, out v3);
|
||
|
|
Console.WriteLine("read cpuid{0:x8}:{1:x8}.{2:x8}.{3:x8}.{4:x8}",
|
||
|
|
reg, v0, v1, v2, v3);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.msrReg != -1) { // read msr.
|
||
|
|
reg = (uint)config.msrReg;
|
||
|
|
if (reg == 0) {
|
||
|
|
Console.WriteLine("Invalid read msr: {0}", reg);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
val = Processor.ReadMsr(reg);
|
||
|
|
Console.WriteLine("read msr{0:x8}:{1:x16}", reg, val);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.writeReg != -1 ) { // write msr.
|
||
|
|
if (config.writeValue == -1) {
|
||
|
|
Console.WriteLine("Invalid write msr: reg={0:x}, value{1:x}", config.writeReg, config.writeValue);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
reg = (uint)config.writeReg;
|
||
|
|
val = (ulong) config.writeValue;
|
||
|
|
Console.WriteLine("write msr{0:x8}:{1:x16}", reg, val);
|
||
|
|
Processor.WriteMsr(reg, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.doDot) { //Simple test.
|
||
|
|
Clear();
|
||
|
|
int yy = 0;
|
||
|
|
int sign = 0;
|
||
|
|
for (int zz = 0; zz < 100000; zz++) {
|
||
|
|
sign *= -1;
|
||
|
|
yy = yy + sign;
|
||
|
|
}
|
||
|
|
DumpNow(true);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.doComma) { //Simple test.
|
||
|
|
Clear();
|
||
|
|
int yy = 0;
|
||
|
|
int sign = 0;
|
||
|
|
for (int zz = 0; zz < 100000; zz++) {
|
||
|
|
sign *= -1;
|
||
|
|
yy = yy + sign;
|
||
|
|
}
|
||
|
|
Thread.Sleep(2);
|
||
|
|
DumpNow(true);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.doZ) { //Simplest test.
|
||
|
|
// Clear the event selectors.
|
||
|
|
Processor.WriteMsr(0xc0010000, 0);
|
||
|
|
Processor.WriteMsr(0xc0010001, 0);
|
||
|
|
// Clear the performance counters.
|
||
|
|
Processor.WriteMsr(0xc0010004, 0);
|
||
|
|
Processor.WriteMsr(0xc0010005, 0);
|
||
|
|
// Enable the event selectors.
|
||
|
|
Processor.WriteMsr(0xc0010000, 0x4f00c0);
|
||
|
|
Processor.WriteMsr(0xc0010001, 0x4f00c2);
|
||
|
|
|
||
|
|
int yy = 0;
|
||
|
|
int sign = 1;
|
||
|
|
for (int zz = 0; zz < 100000; zz++) {
|
||
|
|
sign *= -1;
|
||
|
|
yy = yy + sign;
|
||
|
|
}
|
||
|
|
|
||
|
|
ulong p0 = Processor.ReadPmc(0);
|
||
|
|
ulong p1 = Processor.ReadPmc(1);
|
||
|
|
Console.WriteLine("retired instrcts: {0}", p0);
|
||
|
|
Console.WriteLine("retired branches: {0}", p1);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (false /* FIXFIX need a really long check here */) {
|
||
|
|
DumpNow(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config.doShow /* FIXFIX need a really long check here */) {
|
||
|
|
DumpNow(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|