651 lines
25 KiB
Plaintext
651 lines
25 KiB
Plaintext
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////////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: ProcMemInfo.cs
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//
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//
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// Note: Simple Windows XP-like ProcMemInfo program.
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//
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using System;
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using System.Collections;
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using System.Runtime.CompilerServices;
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using System.Threading;
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using Microsoft.Singularity;
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using Microsoft.Singularity.Channels;
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using Microsoft.Singularity.Diagnostics.Contracts;
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using Microsoft.Singularity.Configuration;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Directory;
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using Microsoft.Singularity.V1.Services;
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using Microsoft.SingSharp;
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using Microsoft.Contracts;
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using Microsoft.SingSharp.Reflection;
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using Microsoft.Singularity.Applications;
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[assembly: Transform(typeof(ApplicationResourceTransform))]
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namespace Microsoft.Singularity.Applications
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{
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[ConsoleCategory(HelpMessage=
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"ProcMemInfo [options] Display Processor Cache info",
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DefaultAction=true)]
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internal sealed class Parameters
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{
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[Endpoint]
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public readonly TRef<UnicodePipeContract.Exp:READY> Stdin;
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[Endpoint]
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public readonly TRef<UnicodePipeContract.Imp:READY> Stdout;
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[Endpoint]
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public readonly TRef<ProcMemInfoContract.Imp:Start> pmInfoRef;
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[BoolParameter( "d", Default=true , HelpMessage=
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"Dumps output and PageTable to Debugger.")]
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internal bool dumpTable;
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reflective internal Parameters();
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internal int AppMain() {
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return ProcMemInfo.AppMain(this);
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}
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}
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public class ProcMemInfo
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{
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// Check if processor is Intel/AMD
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internal static bool isIntel(uint ebx, uint ecx, uint edx)
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{
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) {
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return true;
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}
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else {
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return false;
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}
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}
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// Check if processor is Intel/AMD
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internal static bool isAMD(uint ebx, uint ecx, uint edx)
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{
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if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) {
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return true;
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}
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else {
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return false;
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}
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}
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// Call CPUID with all possible inputs (EAX=1-5,8000_0001-8000_000A)
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internal static void DoTestAllCpuId(Parameters! config)
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{
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bool dumpTable = config.dumpTable;
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uint v0, v1, v2, v3;
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WriteLine(dumpTable, "\n");
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WriteLine(dumpTable, "----------------------------------------");
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WriteLine(dumpTable, "TESTING ALL CPUID ");
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WriteLine(dumpTable, "----------------------------------------\n");
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for (uint i = 0; i < 6; i++) {
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Processor.ReadCpuid(i, out v0, out v1, out v2, out v3);
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WriteLine(dumpTable, "{0:x8} : {1:x8}.{2:x8}.{3:x8}.{4:x8}",
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i, v0, v1, v2, v3);
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}
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for (uint i = 0x80000000; i < 0x80000010; i++) {
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Processor.ReadCpuid(i, out v0, out v1, out v2, out v3);
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WriteLine(dumpTable, "{0:x8} : {1:x8}.{2:x8}.{3:x8}.{4:x8}",
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i, v0, v1, v2, v3);
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}
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WriteLine(dumpTable, "\n");
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}
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// Get AMD Processor Cache Information
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internal static void GetAmdInfo(Parameters! config)
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{
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bool dumpTable = config.dumpTable;
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uint v0, v1, v2, v3;
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WriteLine(dumpTable, "\n");
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WriteLine(dumpTable, "----------------------------------------");
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WriteLine(dumpTable, "PROCESSOR CACHE INFORMATION (from CPUID)");
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WriteLine(dumpTable, "----------------------------------------\n");
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// Call CPUID with Input EAX=1, 8000_0005H and 8000_0006H
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GetAmdInput1(config);
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GetAmdInput85(config);
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GetAmdInput86(config);
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}
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// EAX = 1
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// a : Processor Signature
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// b : Initial APIC ID, CLFLUSH Size, Brand ID
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// c : Reserved
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// d : Standard Feature support
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internal static void GetAmdInput1(Parameters! config)
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{
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uint a, b, c, d;
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uint eax = 1;
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bool dumpTable = config.dumpTable;
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Processor.ReadCpuid(eax, out a, out b, out c, out d);
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// -------------------------------------- output EAX
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uint stepping = (a & 0x0000000f);
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uint model = (a & 0x000000f0) >> 4;
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uint family = (a & 0x00000f00) >> 8;
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uint xModel = (a & 0x000f0000) >> 16;
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uint xFamily = (a & 0x0ff00000) >> 20;
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// from AMD, CPUID manual:
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// computing effective family/model computation
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uint effFamily = family;
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if (family == 0x0f) {
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effFamily = (xFamily + family);
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}
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uint effModel = model;
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if (family == 0x0f) {
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effModel = (xModel << 4) + model;
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}
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/// -------------------------------------- output EBX
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uint brandId = (b & 0x000000ff);
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uint clflush = (b & 0x0000ff00) >> 8;
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uint apicId = (b & 0xff000000) >> 24;
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Write(dumpTable, "\nInput EAX={0:x8} ", eax);
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Write(dumpTable,"output:{1:x8}.{2:x8}.{3:x8}.{4:x8}\n\n",
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eax, a, b, c, d);
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if (a == 0 && b == 0 && c == 0 && d == 0) {
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return;
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}
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WriteLine(dumpTable, " Output EAX:");
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WriteLine(dumpTable, " Stepping {0}", stepping);
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WriteLine(dumpTable, " Model {0}", model);
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WriteLine(dumpTable, " Family {0}", family);
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WriteLine(dumpTable, " xModel {0}", xModel);
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WriteLine(dumpTable, " xFamily {0}", xFamily);
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WriteLine(dumpTable, " effFamily {0}", effFamily);
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WriteLine(dumpTable, " effModel {0}", effModel);
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WriteLine(dumpTable, " Output EBX:");
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WriteLine(dumpTable, " Brand Id {0}", brandId);
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WriteLine(dumpTable, " CLFLUSH Size {0}", clflush);
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WriteLine(dumpTable, " APIC ID {0}", apicId);
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// -------------------------------------- output EDX
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WriteLine(dumpTable, " Output EDX:");
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Write(dumpTable, " ");
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if ((d & 0x1) > 0) { Write(dumpTable, "x87 "); }
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if ((d & 0x2) > 0) { Write(dumpTable, "VME "); }
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if ((d & 0x4) > 0) { Write(dumpTable, "DBG "); }
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if ((d & 0x8) > 0) { Write(dumpTable, "PSE "); }
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if ((d & 0x10) > 0) { Write(dumpTable, "TSC "); }
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if ((d & 0x20) > 0) { Write(dumpTable, "MSR "); }
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if ((d & 0x40) > 0) { Write(dumpTable, "PAE "); }
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if ((d & 0x80) > 0) { Write(dumpTable, "MCE "); }
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Write(dumpTable, "\n ");
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if ((d & 0x100) > 0) { Write(dumpTable, "CX8 "); }
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if ((d & 0x200) > 0) { Write(dumpTable, "APIC "); }
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if ((d & 0x200) > 0) { Write(dumpTable, "R0 "); }
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if ((d & 0x800) > 0) { Write(dumpTable, "SEP "); }
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if ((d & 0x1000) > 0) { Write(dumpTable, "MTRR "); }
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if ((d & 0x2000) > 0) { Write(dumpTable, "PGE "); }
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if ((d & 0x4000) > 0) { Write(dumpTable, "MCA "); }
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if ((d & 0x8000) > 0) { Write(dumpTable, "CMOV "); }
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Write(dumpTable, "\n ");
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if ((d & 0x10000) > 0) { Write(dumpTable, "PAT "); }
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if ((d & 0x20000) > 0) { Write(dumpTable, "P36 "); }
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if ((d & 0x40000) > 0) { Write(dumpTable, "R1 "); }
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if ((d & 0x80000) > 0) { Write(dumpTable, "CFL "); }
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if ((d & 0x100000) > 0) { Write(dumpTable, "R2 "); }
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if ((d & 0x200000) > 0) { Write(dumpTable, "R3 "); }
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if ((d & 0x400000) > 0) { Write(dumpTable, "R4 "); }
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if ((d & 0x800000) > 0) { Write(dumpTable, "MMX "); }
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Write(dumpTable, "\n ");
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if ((d & 0x1000000) > 0) { Write(dumpTable, "FXSR "); }
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if ((d & 0x2000000) > 0) { Write(dumpTable, "SSE "); }
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if ((d & 0x4000000) > 0) { Write(dumpTable, "SSE2 "); }
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if ((d & 0x8000000) > 0) { Write(dumpTable, "R5 "); }
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if ((d & 0x10000000) > 0){ Write(dumpTable, "R6 "); }
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if ((d & 0x20000000) > 0){ Write(dumpTable, "R7 "); }
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if ((d & 0x40000000) > 0){ Write(dumpTable, "R8 "); }
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if ((d & 0x80000000) > 0){ Write(dumpTable, "R9 "); }
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Write(dumpTable, "\n");
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}
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// EAX = 8000_0005
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// a : TLB Bits for 2 MB and 4MB
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// b : TLB Bits for 4 KB
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// c : L1 Data Cache Bits
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// d : L1 Instruction Cache Bits
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internal static void GetAmdInput85(Parameters! config)
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{
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uint a, b, c, d;
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uint eax = 0x80000005;
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bool dumpTable = config.dumpTable;
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Processor.ReadCpuid(eax, out a, out b, out c, out d);
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Write(dumpTable, "\nInput EAX={0:x8} ", eax);
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Write(dumpTable,"output:{1:x8}.{2:x8}.{3:x8}.{4:x8}\n\n",
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eax, a, b, c, d);
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if (a == 0 && b == 0 && c == 0 && d == 0) {
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return;
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}
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uint a1 = (a & 0x000000ff) >> 0;
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uint a2 = (a & 0x0000ff00) >> 8;
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uint a3 = (a & 0x00ff0000) >> 16;
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uint a4 = (a & 0xff000000) >> 24;
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uint b1 = (b & 0x000000ff) >> 0;
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uint b2 = (b & 0x0000ff00) >> 8;
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uint b3 = (b & 0x00ff0000) >> 16;
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uint b4 = (b & 0xff000000) >> 24;
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uint c1 = (c & 0x000000ff) >> 0;
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uint c2 = (c & 0x0000ff00) >> 8;
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uint c3 = (c & 0x00ff0000) >> 16;
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uint c4 = (c & 0xff000000) >> 24;
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uint d1 = (d & 0x000000ff) >> 0;
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uint d2 = (d & 0x0000ff00) >> 8;
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uint d3 = (d & 0x00ff0000) >> 16;
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uint d4 = (d & 0xff000000) >> 24;
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// -------------------------------------- output EAX
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WriteLine(dumpTable, " Output EAX:");
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WriteLine(dumpTable, " 2MB Inst TLB, Entries {0}", a1);
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WriteLine(dumpTable, " 2MB Inst TLB, Assctvy {0}", Assoc(a2));
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WriteLine(dumpTable, " 2MB Data TLB, Entries {0}", a3);
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WriteLine(dumpTable, " 2MB Data TLB, Assctvy {0}", Assoc(a4));
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// -------------------------------------- output EBX
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WriteLine(dumpTable, " Output EBX:");
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WriteLine(dumpTable, " 4KB Inst TLB, Entries {0}", b1);
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WriteLine(dumpTable, " 4KB Inst TLB, Assctvy {0}", Assoc(b2));
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WriteLine(dumpTable, " 4KB Data TLB, Entries {0}", b3);
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WriteLine(dumpTable, " 4KB Data TLB, Assctvy {0}", Assoc(b4));
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// -------------------------------------- output ECX
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WriteLine(dumpTable, " Output ECX:");
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WriteLine(dumpTable, " L1 Data, Line Size {0}", c1);
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WriteLine(dumpTable, " L1 Data, Lines/Tag {0}", c2);
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WriteLine(dumpTable, " L1 Data, Assctvy {0}", Assoc(c3));
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WriteLine(dumpTable, " L1 Data, Size (KB) {0}", c4);
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// -------------------------------------- output EDX
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WriteLine(dumpTable, " Output EDX:");
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WriteLine(dumpTable, " L1 Inst , Line Size {0}", d1);
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WriteLine(dumpTable, " L1 Inst , Lines/Tag {0}", d2);
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WriteLine(dumpTable, " L1 Inst , Assctvy {0}", Assoc(d3));
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WriteLine(dumpTable, " L1 Inst , Size (KB) {0}", d4);
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}
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// Convert associativity code to associativity in string
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internal static string Assoc(uint associativity)
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{
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switch (associativity) {
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case 0: return "Reserved"; break;
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case 1: return "Direct Mapped"; break;
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case 0xff: return "Fully Assoc"; break;
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default :
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return string.Format("{0}-way", associativity);
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break;
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}
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}
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// Similar to Assoc() but specific for L2 cache
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internal static string AssocL2(uint associativity)
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{
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switch (associativity) {
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case 0: return "Off/Disabled"; break;
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case 1: return "Direct Mapped"; break;
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case 0x02: return "2-way"; break;
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case 0x04: return "4-way"; break;
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case 0x06: return "8-way"; break;
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case 0x08: return "16-way"; break;
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case 0x0f: return "Fully Assoc"; break;
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default :
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return "Reserved (disabled?)";
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break;
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}
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}
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// Check if L2 is reserved according to the associativity code
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internal static bool IsL2Reserved(uint associativity)
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{
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switch (associativity)
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{
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case 0:
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case 1:
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case 0x02:
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case 0x04:
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case 0x06:
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case 0x08:
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case 0x0f:
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return false;
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break;
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default :
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return true;
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break;
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}
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}
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// EAX = 8000_0006
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// a : L2 TLB Bits for 2 MB / 4 MB pages
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// b : L2 TLB Bits for 4 KB
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// c : L2 Cache Bits
|
||
|
|
// d : reserved
|
||
|
|
internal static void GetAmdInput86(Parameters! config)
|
||
|
|
{
|
||
|
|
uint a, b, c, d;
|
||
|
|
uint eax = 0x80000006;
|
||
|
|
|
||
|
|
bool dumpTable = config.dumpTable;
|
||
|
|
|
||
|
|
Processor.ReadCpuid(eax, out a, out b, out c, out d);
|
||
|
|
|
||
|
|
uint a1 = (a & 0x000000ff) >> 0;
|
||
|
|
uint a2 = (a & 0x0000ff00) >> 8;
|
||
|
|
uint a3 = (a & 0x00ff0000) >> 16;
|
||
|
|
uint a4 = (a & 0xff000000) >> 24;
|
||
|
|
|
||
|
|
uint b1 = (b & 0x000000ff) >> 0;
|
||
|
|
uint b2 = (b & 0x0000ff00) >> 8;
|
||
|
|
uint b3 = (b & 0x00ff0000) >> 16;
|
||
|
|
uint b4 = (b & 0xff000000) >> 24;
|
||
|
|
|
||
|
|
uint c1 = (c & 0x000000ff) >> 0;
|
||
|
|
uint c2 = (c & 0x0000ff00) >> 8;
|
||
|
|
uint c3 = (c & 0x00ff0000) >> 16;
|
||
|
|
uint c4 = (c & 0xff000000) >> 24;
|
||
|
|
|
||
|
|
Write(dumpTable, "\nInput EAX={0:x8} ", eax);
|
||
|
|
Write(dumpTable,"output:{1:x8}.{2:x8}.{3:x8}.{4:x8}\n\n",
|
||
|
|
eax, a, b, c, d);
|
||
|
|
|
||
|
|
if (a == 0 && b == 0 && c == 0 && d == 0) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
// -------------------------------------- output EAX
|
||
|
|
WriteLine(dumpTable, " Output EAX:");
|
||
|
|
if (a2 == 0) {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Inst TLB is disabled");
|
||
|
|
}
|
||
|
|
else if (IsL2Reserved(a2)) {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Inst TLB is reserved");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Inst TLB, Entries {0}", a1);
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Inst TLB, Assctvy {0}",
|
||
|
|
AssocL2(a2));
|
||
|
|
}
|
||
|
|
if (a4 == 0) {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Data TLB is disabled");
|
||
|
|
}
|
||
|
|
else if (IsL2Reserved(a4)) {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Inst TLB is reserved");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Data TLB, Entries {0}", a3);
|
||
|
|
WriteLine(dumpTable, " 2MB L2 Data TLB, Assctvy {0}",
|
||
|
|
AssocL2(a4));
|
||
|
|
}
|
||
|
|
|
||
|
|
// -------------------------------------- output EBX
|
||
|
|
WriteLine(dumpTable, " Output EBX:");
|
||
|
|
if (b2 == 0) {
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Inst TLB is disabled");
|
||
|
|
}
|
||
|
|
else if (IsL2Reserved(b2)) {
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Inst TLB is reserved");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Inst TLB, Entries {0}", b1);
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Inst TLB, Assctvy {0}",
|
||
|
|
AssocL2(b2));
|
||
|
|
}
|
||
|
|
if (b4 == 0) {
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Data TLB is disabled");
|
||
|
|
}
|
||
|
|
else if (IsL2Reserved(b4))
|
||
|
|
{
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Data TLB is reserved");
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Data TLB, Entries {0}", b3);
|
||
|
|
WriteLine(dumpTable, " 4KB L2 Data TLB, Assctvy {0}",
|
||
|
|
AssocL2(b4));
|
||
|
|
}
|
||
|
|
|
||
|
|
// -------------------------------------- output ECX
|
||
|
|
WriteLine(dumpTable, " Output ECX:");
|
||
|
|
if (c3 == 0)
|
||
|
|
{
|
||
|
|
WriteLine(dumpTable, " L2 Cache is disabled");
|
||
|
|
}
|
||
|
|
else if (IsL2Reserved(c3))
|
||
|
|
{
|
||
|
|
WriteLine(dumpTable, " L2 Cache is reserved");
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
WriteLine(dumpTable, " L2, Line Size {0}", c1);
|
||
|
|
WriteLine(dumpTable, " L2, Lines Per Tag {0}", c2);
|
||
|
|
WriteLine(dumpTable, " L2, Associativity {0}", c3);
|
||
|
|
WriteLine(dumpTable, " L2, Size (KB) {0}", c4);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Call GetCPUID
|
||
|
|
internal static void DoTestGetCpuId(Parameters! config)
|
||
|
|
{
|
||
|
|
bool intel = false, amd = false;
|
||
|
|
uint a, b, c, d;
|
||
|
|
|
||
|
|
Processor.ReadCpuid(0, out a, out b, out c, out d);
|
||
|
|
intel = isIntel(b, c, d);
|
||
|
|
amd = isAMD(b, c, d);
|
||
|
|
|
||
|
|
if (intel) {
|
||
|
|
// haryadi: I haven't implemented Intel config yet
|
||
|
|
// GetIntelInfo(config);
|
||
|
|
}
|
||
|
|
else if (amd) {
|
||
|
|
GetAmdInfo(config);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Get Processor and Memory Affinity
|
||
|
|
internal static void DoTestGetAffinity(Parameters! config)
|
||
|
|
{
|
||
|
|
bool dumpTable = config.dumpTable;
|
||
|
|
ProcMemInfoContract.ProcessorAffinity[] in ExHeap processors;
|
||
|
|
ProcMemInfoContract.MemoryAffinity[] in ExHeap memories;
|
||
|
|
|
||
|
|
ProcMemInfoContract.Imp imp = config.pmInfoRef.Acquire();
|
||
|
|
if (imp == null) {
|
||
|
|
throw new ApplicationException("Error: Unable to bind to " +
|
||
|
|
ProcMemInfoContract.ModuleName);
|
||
|
|
}
|
||
|
|
|
||
|
|
imp.SendGetProcessorAffinity();
|
||
|
|
imp.RecvResultProcessorAffinity(out processors);
|
||
|
|
|
||
|
|
imp.SendGetMemoryAffinity();
|
||
|
|
imp.RecvResultMemoryAffinity(out memories);
|
||
|
|
|
||
|
|
WriteLine(dumpTable, "\n");
|
||
|
|
WriteLine(dumpTable, "----------------------------------------");
|
||
|
|
WriteLine(dumpTable, "PROCESSOR AFFINITY INFORMATION");
|
||
|
|
WriteLine(dumpTable, "----------------------------------------\n");
|
||
|
|
|
||
|
|
if (processors == null) {
|
||
|
|
WriteLine(dumpTable, "There is no Processor Affinity info!");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
WriteLine(dumpTable, "Found {0} processors\n",
|
||
|
|
processors.Length);
|
||
|
|
|
||
|
|
for (int i = 0; i < processors.Length; i++) {
|
||
|
|
WriteLine(dumpTable, "Processor #{0}", i);
|
||
|
|
WriteLine(dumpTable, " domain : {0}",
|
||
|
|
processors[i].domain);
|
||
|
|
WriteLine(dumpTable, " apicId : {0}",
|
||
|
|
processors[i].apicId);
|
||
|
|
WriteLine(dumpTable, " flagIgnore : {0}\n",
|
||
|
|
processors[i].flagIgnore);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
WriteLine(dumpTable, "\n");
|
||
|
|
WriteLine(dumpTable, "----------------------------------------");
|
||
|
|
WriteLine(dumpTable, "MEMORY AFFINITY INFORMATION");
|
||
|
|
WriteLine(dumpTable, "----------------------------------------\n");
|
||
|
|
|
||
|
|
if (memories == null) {
|
||
|
|
WriteLine(dumpTable, "There is no Memory Affinity info!");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
WriteLine(dumpTable, "Found {0} memory\n", memories.Length);
|
||
|
|
|
||
|
|
for (int i = 0; i < memories.Length; i++) {
|
||
|
|
WriteLine(dumpTable, "Memory #{0}", i);
|
||
|
|
WriteLine(dumpTable, " domain : {0}",
|
||
|
|
memories[i].domain);
|
||
|
|
WriteLine(dumpTable, " baseAddress : {0} {1}",
|
||
|
|
GetBigAddr(memories[i].baseAddress),
|
||
|
|
GetBigAddrStr(memories[i].baseAddress));
|
||
|
|
WriteLine(dumpTable, " endAddress : {0} {1}",
|
||
|
|
GetBigAddr(memories[i].endAddress),
|
||
|
|
GetBigAddrStr(memories[i].endAddress));
|
||
|
|
WriteLine(dumpTable, " memorySize : {0} {1}",
|
||
|
|
GetBigAddr(memories[i].memorySize),
|
||
|
|
GetBigAddrStr(memories[i].memorySize));
|
||
|
|
WriteLine(dumpTable, " flagIgnore : {0}",
|
||
|
|
memories[i].flagIgnore);
|
||
|
|
WriteLine(dumpTable, " flagHotPlug : {0}",
|
||
|
|
memories[i].flagHotPluggable);
|
||
|
|
WriteLine(dumpTable, " flagNonVoltl: {0}\n",
|
||
|
|
memories[i].flagNonVolatile);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
delete processors;
|
||
|
|
delete memories;
|
||
|
|
config.pmInfoRef.Release(imp);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
internal static ulong GetBigAddr(ulong address)
|
||
|
|
{
|
||
|
|
ulong KB = 1024;
|
||
|
|
ulong MB = KB * KB;
|
||
|
|
ulong GB = KB * KB * KB;
|
||
|
|
|
||
|
|
if (address > GB) {
|
||
|
|
return address / GB;
|
||
|
|
}
|
||
|
|
else if (address > MB) {
|
||
|
|
return address / MB;
|
||
|
|
}
|
||
|
|
else if (address > KB) {
|
||
|
|
return address / KB;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return address;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
internal static string GetBigAddrStr(ulong address)
|
||
|
|
{
|
||
|
|
ulong KB = 1024;
|
||
|
|
ulong MB = KB * KB;
|
||
|
|
ulong GB = KB * KB * KB;
|
||
|
|
|
||
|
|
if (address > GB) {
|
||
|
|
return "GB";
|
||
|
|
}
|
||
|
|
else if (address > MB) {
|
||
|
|
return "MB";
|
||
|
|
}
|
||
|
|
else if (address > KB) {
|
||
|
|
return "KB";
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return "B";
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Main
|
||
|
|
internal static int AppMain(Parameters! config)
|
||
|
|
{
|
||
|
|
// Set the default options
|
||
|
|
bool dumpTable = config.dumpTable;
|
||
|
|
|
||
|
|
WriteLine(dumpTable, "\nWelcome to ProcMemInfo ... \n\n");
|
||
|
|
|
||
|
|
// Test if ProcMemInfoContract is okay
|
||
|
|
ProcMemInfoContract.Imp imp3 = config.pmInfoRef.Acquire();
|
||
|
|
imp3.RecvReady();
|
||
|
|
config.pmInfoRef.Release(imp3);
|
||
|
|
|
||
|
|
try {
|
||
|
|
DoTestGetAffinity(config);
|
||
|
|
DoTestGetCpuId (config);
|
||
|
|
DoTestAllCpuId (config);
|
||
|
|
} catch (Exception ex) {
|
||
|
|
Console.WriteLine("Error .");
|
||
|
|
Console.WriteLine(ex.ToString());
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/// <summary>
|
||
|
|
/// Use this method to write output to both the screen and the
|
||
|
|
/// debugger if toDebugger is true.
|
||
|
|
/// </summary>
|
||
|
|
public static void WriteLine(bool toDebugger, string format,
|
||
|
|
params object[] args) {
|
||
|
|
string s = String.Format(format, args);
|
||
|
|
Console.WriteLine(s);
|
||
|
|
if (toDebugger) {
|
||
|
|
DebugStub.WriteLine(s);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void Write(bool toDebugger, string format,
|
||
|
|
params object[] args) {
|
||
|
|
string s = String.Format(format, args);
|
||
|
|
Console.Write(s);
|
||
|
|
if (toDebugger) {
|
||
|
|
DebugStub.Write(s);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void WriteLine(bool toDebugger) {
|
||
|
|
Console.WriteLine();
|
||
|
|
if (toDebugger) {
|
||
|
|
DebugStub.WriteLine();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
} // end of ProcMemInfo class
|
||
|
|
} // end of Singularity.Applications
|
||
|
|
|
||
|
|
|
||
|
|
|