243 lines
10 KiB
C#
243 lines
10 KiB
C#
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///////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: NvPciLpcBridge.cs
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//
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// Notes:
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//
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// Driver for Low-Pin Count devices. These are a mix of control
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// registers for legacy and current devices. We currently use it to
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// reroute integrated peripheral interrupts.
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using System;
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using System.Collections;
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using System.Diagnostics;
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using Microsoft.Singularity.Drivers.Pci;
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using Microsoft.Singularity.Channels;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Configuration;
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namespace Microsoft.Singularity.Drivers
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{
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// create the resource object for CTR to fill in
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[DriverCategory]
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[Signature("pci/ven_10de&dev_0050&cc_0601")] // nForce4
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[Signature("pci/ven_10de&dev_0030&cc_0601")] // nForce4 Intel Edition
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[EnumeratesDevice("/pnp/PNP0103")]
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internal class NvPciLpcResources : DriverCategoryDeclaration
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{
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// Provide to unify creation.
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public static IDevice! DeviceCreate(IoConfig! config, string! name)
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{
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return new NvPciLpcBridge((PciDeviceConfig) config);
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}
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}
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public sealed class NvPciLpcBridge : IBusDevice
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{
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private const ushort PCI_VENDOR_NVIDIA = 0x10de;
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private const ushort PCI_DEVICE_NVIDIA_AMD_SATA0 = 0x0054;
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private const ushort PCI_DEVICE_NVIDIA_AMD_SATA1 = 0x0055;
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private const ushort PCI_DEVICE_NVIDIA_AMD_MCP04 = 0x0056;
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private const ushort PCI_DEVICE_NVIDIA_INTEL_SATA0 = 0x0036;
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private const ushort PCI_DEVICE_NVIDIA_INTEL_SATA1 = 0x003e;
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private const ushort PCI_DEVICE_NVIDIA_INTEL_MCP04 = 0x0030;
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private const int PCI_HPET_POINTER = 0x44;
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// Generic PCI interrupt remapping
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private const int PCI_INTERRUPT_MAPPING = 0x7c;
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private const int SATA0_DEVICE_7_ROLL = 24; // Secondary SATA0 IRQ
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private const int SATA1_DEVICE_8_ROLL = 20; // Secondary SATA1 IRQ
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private const int PCI_INTR_Z_ROLL = 12;
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private const int PCI_INTR_Y_ROLL = 8;
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private const int PCI_INTR_X_ROLL = 4;
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private const int PCI_INTR_W_ROLL = 0;
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private const uint PINT_SEL_DISABLE_IRQ = 0x0;
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private const uint PINT_SEL_APIC_IRQ17 = 0x1;
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private const uint PINT_SEL_APIC_IRQ18 = 0x2;
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private const uint PINT_SEL_IRQ3 = 0x3;
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private const uint PINT_SEL_IRQ4 = 0x4;
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private const uint PINT_SEL_IRQ5 = 0x5;
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private const uint PINT_SEL_IRQ6 = 0x6;
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private const uint PINT_SEL_IRQ7 = 0x7;
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private const uint PINT_SEL_APIC_IRQ16 = 0x8;
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private const uint PINT_SEL_IRQ9 = 0x9;
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private const uint PINT_SEL_IRQ10 = 0xa;
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private const uint PINT_SEL_IRQ11 = 0xb;
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private const uint PINT_SEL_IRQ12 = 0xc;
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private const uint PINT_SEL_APIC_IRQ19 = 0xd;
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private const uint PINT_SEL_IRQ14 = 0xe;
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private const uint PINT_SEL_IRQ15 = 0xf;
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// Integrate peripheral mapping
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private const int INTERNAL_IRQ0 = 0x80;
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private const int INTERNAL_IRQ0_SATA0_ROLL = 28; // Primary SATA
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private const int INTERNAL_IRQ0_SATA1_ROLL = 24;
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private const int INTERNAL_IRQ0_P2P_ROLL = 16;
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private const int INTERNAL_IRQ0_USB2_ROLL = 12;
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private const int INTERNAL_IRQ0_SMBUS_ROLL = 8;
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private const int INTERNAL_IRQ0_TCO_ROLL = 4;
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private const int INTERNAL_IRQ0_SCI_ROLL = 0;
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private const int INTERNAL_IRQ1 = 0x84;
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private const int INTERNAL_IRQ1_IDE1_ROLL = 28;
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private const int INTERNAL_IRQ1_IDE0_ROLL = 24;
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private const int INTERNAL_IRQ1_MCI_ROLL = 20;
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private const int INTERNAL_IRQ1_ACI_ROLL = 16;
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private const int INTERNAL_IRQ1_MAC_ROLL = 8;
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private const int INTERNAL_IRQ1_USB0_ROLL = 0;
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private const uint INTERNAL_SEL_DISABLE_IRQ = 0x0;
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private const uint INTERNAL_SEL_APIC_IRQ23 = 0x1;
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private const uint INTERNAL_SEL_APIC_IRQ22 = 0x2;
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private const uint INTERNAL_SEL_IRQ3 = 0x3;
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private const uint INTERNAL_SEL_IRQ4 = 0x4;
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private const uint INTERNAL_SEL_IRQ5 = 0x5;
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private const uint INTERNAL_SEL_IRQ6 = 0x6;
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private const uint INTERNAL_SEL_IRQ7 = 0x7;
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private const uint INTERNAL_SEL_APIC_IRQ20 = 0x8;
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private const uint INTERNAL_SEL_IRQ9 = 0x9;
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private const uint INTERNAL_SEL_IRQ10 = 0xa;
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private const uint INTERNAL_SEL_IRQ11 = 0xb;
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private const uint INTERNAL_SEL_IRQ12 = 0xc;
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private const uint INTERNAL_SEL_APIC_IRQ21 = 0xd;
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private const uint INTERNAL_SEL_IRQ14 = 0xe;
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private const uint INTERNAL_SEL_IRQ15 = 0xf;
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///////////////////////////////////////////////////////////////////////
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PciDeviceConfig! config;
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internal NvPciLpcBridge(PciDeviceConfig! pciDeviceConfig)
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{
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config = pciDeviceConfig;
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}
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void IDevice.Initialize()
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{
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DebugStub.Print("NvPciLpc.Initialize (maxirq={0})\n",
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__arglist(IoSystem.GetMaximumIrq()));
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// Reroute NVidia fixed device resources on APIC system
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if (IoSystem.GetMaximumIrq() > 15)
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{
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ReroutePciInterrupts();
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}
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}
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void IDevice.Finalize()
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{
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}
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private void SetRouteEntry(int register, int roll, uint value)
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{
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DebugStub.Print("NvPciLpc.SetRouteEntry(reg={0},rol={1},val={2})\n",
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__arglist(register, roll, value));
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uint r = config.Read32(register) & ~(0x0fu << roll);
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r |= value << roll;
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config.Write32(register, r);
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}
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private void ReroutePciInterrupts()
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{
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PciEnumerator enumerator = PciEnumerator.GetEnumerator(null);
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ICollection! pciConfigs = enumerator.Enumerate().Values;
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foreach (PciConfig! pc in pciConfigs)
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{
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if (pc.VendorId == PCI_VENDOR_NVIDIA)
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{
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// NB - if there are multiple devices on the bus with the
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// same ID, we still break. Also note that the parameter
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// "1" indicates that this method wants to renumber the 1st
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// Irq in the IoConfig.DynamicRanges list, not the 1st
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// object.
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if ((pc.DeviceId == PCI_DEVICE_NVIDIA_AMD_MCP04 ||
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pc.DeviceId == PCI_DEVICE_NVIDIA_INTEL_MCP04) &&
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IoSystem.RequestRerouteIrq((!)pc.Id, 1, 23))
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{
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SetRouteEntry(INTERNAL_IRQ1, INTERNAL_IRQ1_MAC_ROLL,
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INTERNAL_SEL_APIC_IRQ23);
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pc.SetInterrupt(23);
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}
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else if ((pc.DeviceId == PCI_DEVICE_NVIDIA_AMD_SATA0 ||
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pc.DeviceId == PCI_DEVICE_NVIDIA_INTEL_SATA0) &&
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IoSystem.RequestRerouteIrq((!)pc.Id, 1, 14))
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{
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SetRouteEntry(INTERNAL_IRQ0,
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INTERNAL_IRQ0_SATA0_ROLL,
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INTERNAL_SEL_IRQ14);
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pc.SetInterrupt(14);
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// Map secondary same as primary
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SetRouteEntry(PCI_INTERRUPT_MAPPING,
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SATA0_DEVICE_7_ROLL,
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PINT_SEL_IRQ14);
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}
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else if ((pc.DeviceId == PCI_DEVICE_NVIDIA_AMD_SATA1 ||
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pc.DeviceId == PCI_DEVICE_NVIDIA_INTEL_SATA1) &&
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IoSystem.RequestRerouteIrq((!)pc.Id, 1, 15))
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{
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SetRouteEntry(INTERNAL_IRQ0,
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INTERNAL_IRQ0_SATA1_ROLL,
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INTERNAL_SEL_IRQ15);
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pc.SetInterrupt(15);
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// Map secondary same as primary
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SetRouteEntry(PCI_INTERRUPT_MAPPING,
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SATA1_DEVICE_8_ROLL,
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PINT_SEL_IRQ15);
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}
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}
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}
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}
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public SortedList Enumerate()
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{
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SortedList devs = new SortedList();
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uint hpetPointer = config.Read32(PCI_HPET_POINTER);
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if (hpetPointer != 0)
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{
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IoMemoryRange hpetMemory =
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new IoMemoryRange(hpetPointer, 0x1000,
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Access.ReadWrite);
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devs.Add("/hpet",
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new PnpConfig(new string[] { "/pnp/PNP0103" },
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new IoRange [1] { hpetMemory }
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)
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);
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}
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#if NO
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//
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// XXX sgc compiler does not accept the following preferred
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// means of instantiating a PnpConfig object. It complains:
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//
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// NvPciLpc.cs(189,31): error CS1501:
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// No overload for method 'PnpConfig' takes '2' arguments
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//
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// which is bogus - there are two constructors that take two
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// arguments. They are both public and differ only in their
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// second argument. This is visible in PnpConfig.cs and in
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// the kernel ilasm.
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//
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ArrayList hpetResources = new ArrayList();
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hpetResources.Add(hpetMemory);
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devs.Add("/hpet", new PnpConfig("/PNP0103", hpResources));
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#endif
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return devs;
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}
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}
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}
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