705 lines
26 KiB
C#
705 lines
26 KiB
C#
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///////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: Apic.cs
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//
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//
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// Note:
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// Intel MP Specification 1.4
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// IA-32 Intel Architecture Software Developers Manual
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// Volume 3: Systems Programming Guide
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//
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// Caution:
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// This code has not been tested on multi I/O apic systems
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// and the handling for this case is probably not sane.
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namespace Microsoft.Singularity.Hal
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{
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using System;
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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using Microsoft.Singularity.Io;
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[CLSCompliant(false)]
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internal struct ApicOffset
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{
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internal const uint Id = 0x0020;
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internal const uint Version = 0x0030;
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internal const uint TaskPriority = 0x0080;
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internal const uint ArbitrationPriority = 0x0090;
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internal const uint ProcessorPriority = 0x00a0;
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internal const uint EoiRegister = 0x00b0;
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internal const uint LocalDestination = 0x00d0;
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internal const uint DestinationFormat = 0x00e0;
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internal const uint SpuriousIntVector = 0x00f0;
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internal const uint IsrBase = 0x0100;
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internal const uint TmrBase = 0x0180;
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internal const uint IrrBase = 0x0200;
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internal const uint ErrorStatus = 0x0280;
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internal const uint IcrLo = 0x0300;
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internal const uint IcrHi = 0x0310;
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internal const uint LvtTimer = 0x0320;
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internal const uint LvtThermalSensor = 0x0330;
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internal const uint LvtPerfCounts = 0x0340;
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internal const uint LvtLint0 = 0x0350;
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internal const uint LvtLint1 = 0x0360;
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internal const uint LvtError = 0x0370;
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internal const uint TimerInitialCount = 0x0380;
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internal const uint TimerCurrentCount = 0x0390;
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internal const uint TimerDivideConf = 0x03e0;
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internal const uint Max = 0x0400;
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};
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[CLSCompliant(false)]
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internal struct LvtFlags
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{
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internal const uint TimerBit = 1 << 17;
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internal const uint Periodic = TimerBit;
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internal const uint OneShot = 0;
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internal const uint MaskedBit = 1 << 16;
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internal const uint Masked = MaskedBit;
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internal const uint Unmasked = 0;
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internal const uint TriggerBit = 1 << 15;
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internal const uint Level = TriggerBit;
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internal const uint Edge = 0;
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internal const uint RIRRBit = 1 << 14;
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internal const uint PolarityBit = 1 << 13;
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internal const uint ActiveLow = PolarityBit;
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internal const uint ActiveHigh = 0;
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internal const uint StatusBit = 1 << 12;
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internal const uint Pending = StatusBit;
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internal const uint Idle = 0;
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internal const uint DeliveryBits = 7 << 8;
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internal const uint Fixed = 0 << 8;
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internal const uint SMI = 2 << 8;
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internal const uint NMI = 4 << 8;
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internal const uint INIT = 5 << 8;
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internal const uint ExtInt = 7 << 8;
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}
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[CLSCompliant(false)]
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internal struct IcrFlags
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{
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internal const uint ShorthandBits = 3 << 18;
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internal const uint NoShortHand = 0 << 18;
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internal const uint Self = 1 << 18;
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internal const uint All = 2 << 18;
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internal const uint AllBarSelf = 3 << 18;
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internal const uint TriggerBit = 1 << 15;
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internal const uint Edge = 0;
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internal const uint Level = TriggerBit;
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internal const uint LevelBit = 1 << 14;
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internal const uint DeAssert = 0;
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internal const uint Assert = LevelBit;
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internal const uint StatusBit = 1 << 12;
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internal const uint Idle = 0;
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internal const uint Pending = StatusBit;
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internal const uint ModeBit = 1 << 11;
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internal const uint Physical = 0;
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internal const uint Logical = ModeBit;
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internal const uint DeliveryBits = 7 << 8;
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internal const uint Fixed = 0 << 8;
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internal const uint SMI = 2 << 8;
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internal const uint NMI = 4 << 8;
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internal const uint INIT = 5 << 8;
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internal const uint StartUp = 6 << 8;
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}
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[CLSCompliant(false)]
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public class Apic
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{
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const ushort ImcrAddressPort = 0x22;
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const ushort ImcrDataPort = 0x23;
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const byte ImcrAddressSelect = 0x70;
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const byte ImcrData8259 = 0x00;
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const byte ImcrDataApic = 0x01;
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const byte ApicMSR = 0x1b;
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public const byte RtClockIrq = 8;
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public const byte TimerIrq = 0;
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static uint baseAddr;
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// Table of Apic Ids before changed to cpu-id.
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static byte [] initialIdTable;
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IoMemory apicRegion;
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IoApic [] ioApics;
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byte baseVector;
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byte maxIrq;
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public Apic(IoApic[] ioApics)
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{
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ulong msr = Processor.ReadMsr(0x1b);
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baseAddr = ((uint) msr) & 0xfffff000u;
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this.apicRegion =
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IoMemory.MapPhysicalMemory(baseAddr,
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new UIntPtr(ApicOffset.Max),
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true, true);
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this.ioApics = ioApics;
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DebugStub.Assert(initialIdTable == null); // Check Single Apic instance
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initialIdTable = new byte [256];
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}
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internal void Finalize()
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{
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}
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[NoHeapAllocation]
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internal uint Read(uint offset)
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{
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uint outValue;
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IoResult result = apicRegion.Read32NoThrow((int) offset,
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out outValue);
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DebugStub.Assert(IoResult.Success == result);
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return outValue;
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}
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[NoHeapAllocation]
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internal void Write(uint offset, uint value)
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{
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IoResult result = apicRegion.Write32NoThrow((int) offset, value);
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DebugStub.Assert(IoResult.Success == result);
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}
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internal byte Id
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{
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[NoHeapAllocation]
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get { return (byte)(Read(ApicOffset.Id) >> 24); }
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}
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[NoHeapAllocation]
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private void SetId(byte cpuId)
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{
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uint v = Read(ApicOffset.Id);
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initialIdTable[cpuId] = (byte)(v >> 24);
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v = (v & 0xffffff) | (((uint)cpuId) << 24);
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Write(ApicOffset.Id, v);
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}
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private bool IsBsp
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{
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[NoHeapAllocation]
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get { return (Processor.ReadMsr(0x1b) & 0x100) == 0x100; }
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}
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[NoHeapAllocation]
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private IoApic GetIoApic(int id)
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{
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for (int i = 0; i < ioApics.Length; i++)
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{
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if (ioApics[i].GetId() == id)
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{
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return ioApics[i];
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}
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}
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return null;
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}
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internal void Initialize(byte baseVector)
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{
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DebugStub.Assert(255 - baseVector >= 48);
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this.baseVector = baseVector;
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Write(ApicOffset.LvtTimer, LvtFlags.Masked);
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Write(ApicOffset.LvtThermalSensor, LvtFlags.Masked);
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Write(ApicOffset.LvtPerfCounts, LvtFlags.Masked);
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Write(ApicOffset.LvtError, LvtFlags.Masked);
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Write(ApicOffset.SpuriousIntVector, 0xdfu);
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// haryadi -- set task priority to 0 so that it can
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// receive all interrupts from IPI
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// Write(ApicOffset.TaskPriority, 0x20u);
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Write(ApicOffset.TaskPriority, 0);
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Write(ApicOffset.LvtLint0, LvtFlags.Masked);
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Write(ApicOffset.LvtLint1, LvtFlags.Masked);
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SetId((byte) Processor.GetCurrentProcessorId());
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if (this.IsBsp) {
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InitializeRouteableEntries();
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InitializeMpResourceEntries();
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}
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// Enable in s/w
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SetEnabled(true);
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// Enable in h/w
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Processor.WriteMsr(ApicMSR, Processor.ReadMsr(ApicMSR) | (1 << 11));
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// Watch out for the uniprocessor case where the
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// FloatingPointer may be null.
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MpFloatingPointer floatingPointer = MpResources.FloatingPointer;
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if (floatingPointer != null && floatingPointer.ImcrPresent && this.IsBsp) {
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IoPort addrPort = new IoPort(ImcrAddressPort, 1, Access.Write);
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IoPort dataPort = new IoPort(ImcrDataPort, 1, Access.Write);
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addrPort.Write8(ImcrAddressSelect);
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dataPort.Write8(ImcrDataApic);
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}
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Write(ApicOffset.LvtLint0, LvtFlags.Level | LvtFlags.ExtInt);
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Write(ApicOffset.LvtLint1, LvtFlags.NMI | 0x02);
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for (int z = 0; z <= maxIrq; z++) {
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byte m = IrqToInterrupt((byte) z);
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byte n = InterruptToIrq(m);
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DebugStub.Assert((byte) z == n);
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}
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}
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internal void Initialize()
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{
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Initialize(0x70);
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}
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private void InitializeRouteableEntries()
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{
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// Initialize entries that may not be part of MP set
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// configuration, but might be utilizable via a
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// programmable interrupt routing on PCI-LPC bridge
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// or elsewhere.
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byte irq = 16;
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IoBits stdPciBits = (IoBits.DstPhysical | IoBits.DelModFixed |
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IoBits.IrqMask | IoBits.IntPolActiveLow |
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IoBits.TriggerModeLevel);
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for (int id = 0; id < ioApics.Length; id++) {
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uint start = (id == 0) ? 16u : 0u;
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uint end = ioApics[id].RedirectionEntryCount;
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for (uint index = start; index < end; index++) {
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RedirectionEntry re =
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new RedirectionEntry(this.Id, stdPciBits,
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IrqToInterrupt(irq));
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ioApics[id].SetRedirectionEntry(index, ref re);
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irq++;
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}
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}
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maxIrq = (byte) (irq - 1);
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}
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private void InitializeMpResourceEntries()
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{
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foreach (MpInterruptEntry e in MpResources.IoInterruptEntries) {
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IoApic ioApic = GetIoApic(e.ApicId);
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if (ioApic == null) {
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DebugStub.Print("Could not find I/O Apic with id {0}\n",
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__arglist(e.ApicId));
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continue;
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}
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MpBusEntry be = MpResources.GetBusEntryById(e.BusId);
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if (be == null) {
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DebugStub.Print("Unknown bus device id {0:x2}\n",
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__arglist(e.BusId));
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continue;
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}
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if (be.BusType == BusType.ISA) {
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ConfigureIsaInterrupt(ioApic, e);
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}
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else if (be.BusType == BusType.PCI) {
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ConfigurePciInterrupt(ioApic, e);
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}
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else {
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DebugStub.Print("Unhandled device on bus {0:x2}\n",
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__arglist(e.BusId));
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continue;
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}
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}
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}
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internal void ConfigureIsaInterrupt(IoApic ioApic, MpInterruptEntry e)
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{
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byte vector = IrqToInterrupt(e.BusIrq);
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IoBits iobits = (e.PolarityType == Polarity.ActiveLow) ?
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IoBits.IntPolActiveLow : IoBits.IntPolActiveHigh;
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iobits |= (e.TriggerType == Trigger.Level) ?
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IoBits.TriggerModeLevel : IoBits.TriggerModeEdge;
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iobits |= IoBits.DstPhysical;
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iobits |= IoBits.DelModFixed;
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iobits |= IoBits.IrqMask;
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RedirectionEntry r = new RedirectionEntry(this.Id, iobits, vector);
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ioApic.SetRedirectionEntry(e.ApicLine, ref r);
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}
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internal void ConfigurePciInterrupt(IoApic ioApic, MpInterruptEntry e)
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{
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byte vector = IrqToInterrupt(e.ApicLine);
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IoBits iobits = (e.PolarityType == Polarity.ActiveHigh) ?
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IoBits.IntPolActiveHigh : IoBits.IntPolActiveLow;
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iobits |= (e.TriggerType == Trigger.Edge) ?
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IoBits.TriggerModeEdge : IoBits.TriggerModeLevel;
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iobits |= IoBits.DstPhysical;
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iobits |= IoBits.DelModFixed;
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iobits |= IoBits.IrqMask;
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RedirectionEntry r = new RedirectionEntry(this.Id, iobits, vector);
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ioApic.SetRedirectionEntry(e.ApicLine, ref r);
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}
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[NoHeapAllocation]
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public byte InterruptToIrq(byte interrupt)
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{
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if (interrupt < baseVector) {
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return RtClockIrq;
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}
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if (interrupt == baseVector) {
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return TimerIrq;
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}
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if (interrupt == baseVector + 16) {
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return RtClockIrq;
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}
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return (byte)(interrupt - (baseVector + 32));
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}
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[NoHeapAllocation]
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public byte IrqToInterrupt(byte irq)
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{
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if (irq == TimerIrq) {
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return (byte) (baseVector + 0);
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}
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if (irq == RtClockIrq) {
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return (byte) (baseVector + 16);
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}
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return (byte) (baseVector + 32 + irq);
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}
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|
|
public byte MaximumIrq
|
||
|
|
{
|
||
|
|
[NoHeapAllocation]
|
||
|
|
get { return maxIrq; }
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public void SetEnabled(bool enabled)
|
||
|
|
{
|
||
|
|
uint v = Read(ApicOffset.SpuriousIntVector);
|
||
|
|
v &= ~(1u << 8);
|
||
|
|
if (enabled)
|
||
|
|
v |= 1u << 8;
|
||
|
|
Write(ApicOffset.SpuriousIntVector, v);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public bool GetEnabled()
|
||
|
|
{
|
||
|
|
return (Read(ApicOffset.SpuriousIntVector) & (1u << 8)) != 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public void AckIrq(byte irq)
|
||
|
|
{
|
||
|
|
// XXX should not ack spurious interrupt
|
||
|
|
Write(ApicOffset.EoiRegister, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public void EnableIrq(byte irq)
|
||
|
|
{
|
||
|
|
// XXX TODO fix for multiple I/O apics
|
||
|
|
ioApics[0].SetEntryMask(irq, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public void DisableIrq(byte irq)
|
||
|
|
{
|
||
|
|
// XXX TODO fix for multiple I/O apics
|
||
|
|
ioApics[0].SetEntryMask(irq, true);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
public void ClearInterrupt(byte interrupt)
|
||
|
|
{
|
||
|
|
byte irq = InterruptToIrq(interrupt);
|
||
|
|
Tracing.Log(Tracing.Debug, "Clearing interrupt {0} (irq {1})",
|
||
|
|
(UIntPtr)interrupt, (UIntPtr)irq);
|
||
|
|
// byte isrInterrupt = (byte) ActiveIsrInterrupt();
|
||
|
|
if (interrupt >= baseVector) {
|
||
|
|
// DebugStub.Assert(interrupt == isrInterrupt);
|
||
|
|
DisableIrq(irq);
|
||
|
|
}
|
||
|
|
AckIrq(irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private bool SendIPI(uint icrHi, uint icrLo)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// DebugStub.Print is not permitted here. We may be
|
||
|
|
// invoked from within DebugStub.Trap with the
|
||
|
|
// non-recursive communication lock held.
|
||
|
|
//
|
||
|
|
Tracing.Log(Tracing.Audit,
|
||
|
|
"Sending IPI {0:x8}{1:x8}\n", icrHi, icrLo);
|
||
|
|
|
||
|
|
// Clear ESR
|
||
|
|
Write(ApicOffset.ErrorStatus, 0);
|
||
|
|
Write(ApicOffset.ErrorStatus, 0);
|
||
|
|
|
||
|
|
// Send IPI
|
||
|
|
Write(ApicOffset.IcrHi, icrHi);
|
||
|
|
Write(ApicOffset.IcrLo, icrLo);
|
||
|
|
|
||
|
|
do {
|
||
|
|
Write(ApicOffset.ErrorStatus, 0); // Trigger ESR update
|
||
|
|
uint esr = Read(ApicOffset.ErrorStatus);
|
||
|
|
if (esr != 0) {
|
||
|
|
Tracing.Log(Tracing.Warning,
|
||
|
|
"APIC SendIPI Error (esr = {0})\n", esr);
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
} while ((Read(ApicOffset.IcrLo) & IcrFlags.Pending) != 0);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private static void Delay(uint micros)
|
||
|
|
{
|
||
|
|
HalDevices.StallProcessor(micros);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void BroadcastStartupIPI(byte vector)
|
||
|
|
{
|
||
|
|
Write(ApicOffset.IcrHi, 0);
|
||
|
|
|
||
|
|
// Per AP initialization in IA-32 Vol 3
|
||
|
|
// Init IPI // ICR.Lo = 00c4500h
|
||
|
|
SendIPI(0, IcrFlags.AllBarSelf | IcrFlags.Assert | IcrFlags.Pending | IcrFlags.INIT | (uint)vector);
|
||
|
|
|
||
|
|
// ...delay 10ms
|
||
|
|
Delay(10000);
|
||
|
|
|
||
|
|
// Startup IPI // ICR.Lo = 00c46XXh
|
||
|
|
SendIPI(0, IcrFlags.AllBarSelf | IcrFlags.Assert | IcrFlags.Pending | IcrFlags.StartUp | (uint)vector);
|
||
|
|
|
||
|
|
// ...delay 200us
|
||
|
|
Delay(200);
|
||
|
|
SendIPI(0,
|
||
|
|
(IcrFlags.AllBarSelf | IcrFlags.Assert | IcrFlags.Pending |
|
||
|
|
IcrFlags.StartUp | (uint)vector)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void BroadcastFreezeIPI()
|
||
|
|
{
|
||
|
|
Write(ApicOffset.IcrHi, 0);
|
||
|
|
SendIPI(0,
|
||
|
|
(IcrFlags.AllBarSelf | IcrFlags.Assert |
|
||
|
|
IcrFlags.Pending | IcrFlags.NMI)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void SendFixedIPI(byte vector, int from, int to)
|
||
|
|
{
|
||
|
|
uint icrHi = ((uint)to & 0x0ff) << 24;
|
||
|
|
uint icrLo =
|
||
|
|
IcrFlags.NoShortHand | IcrFlags.Assert |
|
||
|
|
IcrFlags.Pending | IcrFlags.Fixed |
|
||
|
|
IcrFlags.Physical | (uint)vector;
|
||
|
|
|
||
|
|
Write(ApicOffset.IcrHi, 0);
|
||
|
|
|
||
|
|
if (!SendIPI(icrHi, icrLo)) {
|
||
|
|
DebugStub.Break();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void BroadcastFixedIPI(byte vector, bool includeSelf)
|
||
|
|
{
|
||
|
|
uint icrHi = 0;
|
||
|
|
uint icrLo = includeSelf ? IcrFlags.All : IcrFlags.AllBarSelf;
|
||
|
|
icrLo |= (IcrFlags.Assert | IcrFlags.Pending | IcrFlags.Fixed |
|
||
|
|
(uint)vector);
|
||
|
|
|
||
|
|
Write(ApicOffset.IcrHi, 0);
|
||
|
|
|
||
|
|
if (!SendIPI(icrHi, icrLo)) {
|
||
|
|
DebugStub.Break();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void ClearFixedIPI()
|
||
|
|
{
|
||
|
|
Write(ApicOffset.EoiRegister, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private bool IrrIsSet(byte interrupt)
|
||
|
|
{
|
||
|
|
// Read() is 4 bytes wide.
|
||
|
|
// Each DWORD is aligned on 16-byte boundaries.
|
||
|
|
// IsrBase + 0x00 = interrupts 0-31
|
||
|
|
// IsrBase + 0x10 = interrupts 32-63
|
||
|
|
// IsrBase + 0x20 = interrupts 64-95
|
||
|
|
// ...
|
||
|
|
// IsrBase + 0x70 = interrupts 224-255
|
||
|
|
uint d = (uint)interrupt / 32u;
|
||
|
|
uint o = ApicOffset.IrrBase + d * 16u;
|
||
|
|
uint m = 1u << (int) ((int)interrupt - d * 32);
|
||
|
|
return (Read(o) & m) == m;
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private bool IsrIsSet(byte interrupt)
|
||
|
|
{
|
||
|
|
// Read() is 4 bytes wide.
|
||
|
|
// Each DWORD is aligned on 16-byte boundaries.
|
||
|
|
// IsrBase + 0x00 = interrupts 0-31
|
||
|
|
// IsrBase + 0x10 = interrupts 32-63
|
||
|
|
// IsrBase + 0x20 = interrupts 64-95
|
||
|
|
// ...
|
||
|
|
// IsrBase + 0x70 = interrupts 224-255
|
||
|
|
uint d = (uint)interrupt / 32u;
|
||
|
|
uint o = ApicOffset.IsrBase + d * 16u;
|
||
|
|
uint m = 1u << (int) ((int)interrupt - d * 32);
|
||
|
|
return (Read(o) & m) == m;
|
||
|
|
}
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private uint Log2(uint value)
|
||
|
|
{
|
||
|
|
uint l = 0;
|
||
|
|
if ((value & 0xffff0000u) != 0) l += 16u;
|
||
|
|
if ((value & 0xff00ff00u) != 0) l += 8u;
|
||
|
|
if ((value & 0xf0f0f0f0u) != 0) l += 4u;
|
||
|
|
if ((value & 0xccccccccu) != 0) l += 2u;
|
||
|
|
if ((value & 0xaaaaaaaau) != 0) l += 1u;
|
||
|
|
return l;
|
||
|
|
}
|
||
|
|
|
||
|
|
private uint lastByte;
|
||
|
|
private int lastByteValue;
|
||
|
|
private uint lastIsr;
|
||
|
|
|
||
|
|
[NoHeapAllocation]
|
||
|
|
private uint ActiveIsrInterrupt()
|
||
|
|
{
|
||
|
|
uint isr = ~0u;
|
||
|
|
uint i;
|
||
|
|
for (i = 0; i < 0x80; i += 0x10) {
|
||
|
|
uint value = Read(ApicOffset.IsrBase + i);
|
||
|
|
if (value != 0) {
|
||
|
|
lastByteValue = (int) value;
|
||
|
|
lastByte = i;
|
||
|
|
DebugStub.Assert((value & (value - 1)) == 0);
|
||
|
|
isr = i * 2 + Log2(value);
|
||
|
|
lastIsr = isr;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
i += 0x10;
|
||
|
|
for (; i < 0x80; i += 0x10) {
|
||
|
|
uint value = Read(ApicOffset.IsrBase + i);
|
||
|
|
DebugStub.Assert(value == 0);
|
||
|
|
}
|
||
|
|
DebugStub.Assert(isr != ~0u);
|
||
|
|
return isr;
|
||
|
|
}
|
||
|
|
|
||
|
|
[Conditional("DEBUG_APIC")]
|
||
|
|
[NoHeapAllocation]
|
||
|
|
internal void DumpState()
|
||
|
|
{
|
||
|
|
ulong msr = Processor.ReadMsr(0x1b);
|
||
|
|
uint baseAddr = ((uint) msr) & 0xfffff000u;
|
||
|
|
uint en = (((uint) msr) >> 11) & 0x1;
|
||
|
|
uint bsp = (((uint) msr) >> 8) & 0x1;
|
||
|
|
|
||
|
|
DebugStub.Print("Apic Base {0:x8} MSR Enabled {1} BSP {2}\n",
|
||
|
|
__arglist(baseAddr, en, bsp));
|
||
|
|
|
||
|
|
DebugStub.Print("Id {0:x} Version {1:x} TaskPriority {2:x} " +
|
||
|
|
"ArbitrationPriority {3:x} ProcessorPriority {4:x}\n",
|
||
|
|
__arglist(
|
||
|
|
Read(ApicOffset.Id),
|
||
|
|
Read(ApicOffset.Version),
|
||
|
|
Read(ApicOffset.TaskPriority),
|
||
|
|
Read(ApicOffset.ArbitrationPriority),
|
||
|
|
Read(ApicOffset.ProcessorPriority)));
|
||
|
|
|
||
|
|
DebugStub.Print("Timer LVT {0:x8} Thermal LVT {1:x8} " +
|
||
|
|
"PerfCounts LVT {2:x8}\n",
|
||
|
|
__arglist(
|
||
|
|
Read(ApicOffset.LvtTimer),
|
||
|
|
Read(ApicOffset.LvtThermalSensor),
|
||
|
|
Read(ApicOffset.LvtPerfCounts)));
|
||
|
|
|
||
|
|
DebugStub.Print("Lint0 LVT {0:x8} Lint1 LVT {1:x8}\n",
|
||
|
|
__arglist(
|
||
|
|
Read(ApicOffset.LvtLint0),
|
||
|
|
Read(ApicOffset.LvtLint1)));
|
||
|
|
|
||
|
|
DebugStub.Print("LvtError LVT {0:x8} Spurious LVT {1:x8} ESR {2:x2}\n",
|
||
|
|
__arglist(
|
||
|
|
Read(ApicOffset.LvtError),
|
||
|
|
Read(ApicOffset.SpuriousIntVector),
|
||
|
|
Read(ApicOffset.ErrorStatus) & 0xef));
|
||
|
|
}
|
||
|
|
|
||
|
|
// haryadi -- print IRR and ISR register
|
||
|
|
#if FALSE
|
||
|
|
// : This method is commented out because
|
||
|
|
// it allocates memory. The fix is trivial.
|
||
|
|
internal void PrintIrrAndIsr(bool debug)
|
||
|
|
{
|
||
|
|
uint addr, a;
|
||
|
|
uint [] c = new uint [8];
|
||
|
|
uint [] b = new uint [8];
|
||
|
|
|
||
|
|
if (debug) {
|
||
|
|
DebugStub.Print("HSG: IRR ");
|
||
|
|
for (int i = 0; i < 8; i++) {
|
||
|
|
addr = ApicOffset.IrrBase+(uint)(i*32);
|
||
|
|
a = Read(addr);
|
||
|
|
DebugStub.Print("{0}.{1:x08} ", __arglist(i,a));
|
||
|
|
}
|
||
|
|
DebugStub.WriteLine("");
|
||
|
|
DebugStub.Print("HSG: ISR ");
|
||
|
|
for (int i = 0; i < 8; i++) {
|
||
|
|
addr = ApicOffset.IsrBase+(uint)(i*32);
|
||
|
|
a = Read(addr);
|
||
|
|
DebugStub.Print("{0}.{1:x08} ", __arglist(i,a));
|
||
|
|
}
|
||
|
|
DebugStub.WriteLine("");
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
for (int i = 0; i < 8; i++) {
|
||
|
|
addr = ApicOffset.IrrBase+(uint)(i*32);
|
||
|
|
c[i] = Read(addr);
|
||
|
|
}
|
||
|
|
for (int i = 0; i < 8; i++) {
|
||
|
|
addr = ApicOffset.IsrBase+(uint)(i*32);
|
||
|
|
b[i] = Read(addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
Tracing.Log(Tracing.Debug, "************************************");
|
||
|
|
Tracing.Log(Tracing.Debug, "IRR lo: {0:x08} {1:x08} {2:x08} {3:x08}",
|
||
|
|
c[0], c[1], c[2], c[3]);
|
||
|
|
Tracing.Log(Tracing.Debug, "IRR hi: {0:x08} {1:x08} {2:x08} {3:x08}",
|
||
|
|
c[4], c[5], c[6], c[7]);
|
||
|
|
Tracing.Log(Tracing.Debug, "ISR lo: {0:x08} {1:x08} {2:x08} {3:x08}",
|
||
|
|
b[0], b[1], b[2], b[3]);
|
||
|
|
Tracing.Log(Tracing.Debug, "ISRb hi: {0:x08} {1:x08} {2:x08} {3:x08}",
|
||
|
|
b[4], b[5], b[6], b[7]);
|
||
|
|
|
||
|
|
}
|
||
|
|
#endif // FALSE
|
||
|
|
}
|
||
|
|
}
|