446 lines
11 KiB
NASM
446 lines
11 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; except.s
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;
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; Copyright (C) Advanced RISC Machines Limited, 1994. All rights reserved.
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;
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; RCS Revision: 1
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; Checkin Date: 2007/06/29 02:59:16
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; Revising Author
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;==============================================================================
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;Error generation - from ANSI library
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GET fpe.asm
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GET h_errors.asm
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[ :DEF: liberror_s
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AREA |.text|, CODE, READONLY
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Export_32 __fp_edom
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Export_32 __fp_erange
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; __fp_edom(ulong sign_bit, boolean huge_val);
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; __fp_erange(ulong sign_bit, boolean huge_val);
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;
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; set errno to EDOM/ERANGE and return sign_bit | (huge_val ? HUGE_VAL : 0)
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__fp_edom EnterWithLR
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MOV a3, #EDOM
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B skip
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__fp_erange EnterWithLR
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MOV a3, #ERANGE
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skip
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AND a4, a1, #Sign_bit
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[ :DEF:EMBEDDED_CLIB
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IMPORT __rt_errno_addr
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LDR a1, =__rt_errno_addr
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CMP a1, #0
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BEQ %FT1
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STMDB sp!, {a2-a4, lr}
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BL __rt_errno_addr
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LDMIA sp!, {a2-a4, lr}
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STR a3, [a1]
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1
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LDR a1, errno
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STR a3, [a1]
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]
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TEQ a2, #0
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MOVEQ a1, #0 ; generate +/- 0.0 in a1/a2
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LDRNE a1, huge_val
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LDMNEIA a1, {a1, a2} ; load HUGE_VAL into a1/a2
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ORR a1, a1, a4 ; add in sign bit
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ReturnToLR
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[ :LNOT::DEF:EMBEDDED_CLIB
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errno
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IMPORT __errno
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DCD __errno
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]
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huge_val
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IMPORT __huge_val
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DCD __huge_val
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]
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;==============================================================================
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;Setting/returning status flags.
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[ :DEF: status_s
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AREA |.text|, CODE, READONLY
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EXPORT __fp_status
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; extern unsigned int __fp_status(unsigned int mask,unsigned int flags)
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__fp_status
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[ :DEF: thumb
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CODE16
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; mask "mask" to an acceptable value
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MOV a4,#&e0
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LSL a3,a1,#32-FPExceptE_pos-Except_len
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LSR a3,a3,#32-FPExceptE_pos-Except_len
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BIC a3,a4
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LSR a4,#8
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BIC a3,a4
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AND a4,a1
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ORR a3,a1
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AND a2,a3
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; mask in a3, masked flags in a2
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LDR a4,status_ptr
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LDR a1,[a4]
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; **** *WARNING* is ip spare under the TPCS ????? ****
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MOV ip,a1 ; store value
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BIC a1,a3
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EOR a1,a2
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STR a1,[a4]
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MOV a1,ip ; restore value
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BX lr
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ALIGN
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; mask "mask" to an acceptable value
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MOV a3,a1,LSL #32-FPExceptE_pos-Except_len
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BIC a3,a3,#&e0:SHL:(32-FPExceptE_pos-Except_len)
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BIC a3,a3,#&e0:SHL:(32-FPExceptE_pos-Except_len+8)
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AND a2,a2,a3,LSR #32-FPExceptE_pos-Except_len
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; mask in a3, masked flags in a2.
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LDR a4,status_ptr
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LDR a1,[a4] ; load old flags
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BIC a3,a1,a3,LSR #32-FPExceptE_pos-Except_len
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EOR a3,a3,a2 ; clear/set/toggle flags and
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STR a3,[a4] ; write back.
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IF Interworking :LOR: Thumbing
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BX lr
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ELSE
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MOV pc,lr ; return
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ENDIF
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]
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status_ptr
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IMPORT __fp_status_flags
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DCD __fp_status_flags
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]
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;==============================================================================
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;Error checking - from fplib code
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[ :DEF: fcheck_s
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AREA |.text|, CODE, READONLY
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[ :DEF: thumb
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CODE32
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]
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EXPORT __fp_fcheck_NaN2
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EXPORT __fp_dcheck_NaN2
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EXPORT __fp_return_NaN
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EXPORT __fp_return_Inf
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IMPORT __fp_exception
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; Check fOP1 and fOP2 for signalling NaN, IP contains exception flags.
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__fp_fcheck_NaN2
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MOV a4, #0x01000000
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CMN a4, fOP1, LSL #1
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BLS fcheck_opnd2_NaN
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fcheck_opnd1_NaN
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TST fOP1, #fSignalBit
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BEQ __fp_exception
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CMN a4, fOP2, LSL #1
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BLS __fp_return_NaN
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fcheck_opnd2_NaN
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MOV fOP1, fOP2
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TST fOP1, #fSignalBit
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BNE __fp_return_NaN ;; RDCFix: Do we really want to do this?
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; BEQ __fp_return_NaN
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B __fp_exception
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; Check dOP1 and dOP2 for signalling NaN, IP contains exception flags.
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__fp_dcheck_NaN2
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STMFD sp!, {ip}
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MOV tmp, #0x00200000
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CMN tmp, dOP1h, LSL #1
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CMPEQ dOP1l, #0
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BLS dcheck_opnd2_NaN
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dcheck_opnd1_NaN
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TST dOP1h, #dSignalBit
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LDMEQFD sp!, {ip}
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BEQ __fp_exception
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CMN tmp, dOP2h, LSL #1
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CMPEQ dOP2l, #0
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LDMLSFD sp!, {ip}
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BLS __fp_return_NaN
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dcheck_opnd2_NaN
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LDMFD sp!, {ip}
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MOV dOP1h, dOP2h
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MOV dOP1l, dOP2l
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TST dOP1h, #dSignalBit
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BNE __fp_return_NaN ;; RDCFix: Do we really want to do this?
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; BEQ __fp_return_NaN
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B __fp_exception
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; Return NaN in fOP / dOP, except for non-float returning functions.
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; IP contains exception flags.
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__fp_return_NaN
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; test for special cases
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;;
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;; RDCFix: Will need to fix this once new defines are in. May want to
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;; do some performance enhancements to keep from needing to check
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;; each _Fp* operation code. Maybe a jump table. Maybe forget
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;; this garbage and make the core emulation routines pack up
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;; their proper results instead of hacking them up here.
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;;
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; AND a4, ip, #Fn_mask
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; CMP a4, #CompareFalseFn
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; CMPNE a4, #FixZeroFn
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; BEQ return_zero
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; CMP a4, #CompareTrueFn
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; BEQ return_one
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; CMP a4, #CmpLessFn
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; BEQ return_HI
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; CMP a4, #CmpGreaterFn
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; BEQ return_LO
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; CMP a4, #CmpEqualFn
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; BEQ return_NE
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; CMP a4, #FixFn
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; BEQ return_smaxint
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; CMP a4, #FixuFn
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; BEQ return_umaxint
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ReturnToLR
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return_HI
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MOV a1, #1
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CMP a1, #0
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ReturnToLR_flg
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return_LO
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MOV a1, #0
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CMP a1, #1
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ReturnToLR_flg
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return_NE
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MOVS a1, #1
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ReturnToLR_flg
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return_one
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MOV a1, #1
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ReturnToLR
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return_zero
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MOV a1, #0
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MOV a2, #0
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ReturnToLR
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return_smaxint
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MOV a3, a1
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TST ip, #LongLong_bit
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MOVEQ a1, #0x7fffffff
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MOVNE a1, #0xffffffff
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MOVNE a2, #0x7fffffff
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TST a3, #Sign_bit
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MVNNE a1, a1
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MVNNE a2, a2
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ReturnToLR
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return_umaxint
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MOV a1, #0xffffffff
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MOV a2, #0xffffffff
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ReturnToLR
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__fp_return_Inf
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; no special cases
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ReturnToLR
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]
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;==============================================================================
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;Error generation - from fplib code
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[ :DEF: except_s
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AREA |.text|, CODE, READONLY
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; SWI Names
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[ :DEF: thumb
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CODE32
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]
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EXPORT __fp_veneer_error
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EXPORT __fp_nonveneer_error
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EXPORT __fp_exception
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IMPORT __fp_return_NaN
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IMPORT __fp_return_Inf
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__fp_veneer_error ; a4 contains the exception flags
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__fp_nonveneer_error ; a4 contains the exception flags OBSOLETE
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MOV ip, a4
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; fallthrough
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; fp_exception is called when an IEEE exception has occurred
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; a1 contains the sign of the NaN to be returned if the exception is disabled
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; ip contains the exception flags (see fpe.s for a list)
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__fp_exception
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IMPORT FPE_Raise
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STMDB sp!,{lr}
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TST ip,#OVF_bit
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BNE overflow
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TST ip,#UNF_bit
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BNE underflow
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TST ip,#DVZ_bit
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BNE divide_by_zero
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TST ip,#INX_bit
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BNE divide_by_zero
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invalid_operation
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BL return_NaN
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B callraise
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overflow
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BL return_Inf
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B callraise
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underflow
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MOV a1, #0
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MOV a2, #0
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B callraise
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inexact
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B callraise
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divide_by_zero
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BL return_Inf
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callraise
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {lr}
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BX lr
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ELSE
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LDMIA sp!, {pc}
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ENDIF
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;GenerateError
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; IMPORT RaiseException
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; [ :DEF:EMBEDDED_CLIB
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; STMDB sp!, {r0-r15}
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; SUB lr, lr, #4
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; STR lr, [sp, #15*4]
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; MOV r1, sp
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; |
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; LDR r1,ErrBlock
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; SUB lr,lr,#4
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; STR lr,[r1,#15*4]
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; MOV lr,#&de00
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; ORR lr,lr,#&00ad
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; ORR lr,lr,lr,LSL #16
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; STMIA r1,{r0-r14}
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; B RaiseException
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status_ptr
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IMPORT __fp_status_flags
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DCD __fp_status_flags
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ErrBlock
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IMPORT __fp_errblock
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DCD __fp_errblock
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trap
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; ]
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IMPORT __rt_trap
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LDR ip, =__rt_trap
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CMP ip, #0
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[ Interworking :LOR:(:DEF:thumb)
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BXNE ip
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MOVNE pc, ip
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]
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DCD 0xe6000010
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ErrorBlock FP_IVO, "Floating Point Exception: Invalid Operation"
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ErrorBlock FP_OFL, "Floating Point Exception: Overflow"
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ErrorBlock FP_DVZ, "Floating Point Exception: Divide By Zero"
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return_Inf
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AND a3,a1,#Sign_bit
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TST ip,#Double_bit
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ADRNE a1,prototype_double_Inf
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LDMNEIA a1,{a1,a2}
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LDREQ a1,prototype_single_Inf
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ORR a1,a1,a3
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B __fp_return_Inf
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return_NaN
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AND a3, a1, #Sign_bit
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TST ip, #Double_bit
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ADRNE a1,prototype_double_NaN
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||
|
|
LDMNEIA a1,{a1,a2}
|
||
|
|
LDREQ a1,prototype_single_NaN
|
||
|
|
ORR a1, a1, a3
|
||
|
|
B __fp_return_NaN
|
||
|
|
|
||
|
|
prototype_double_Inf
|
||
|
|
DCD &7ff00000,&00000000
|
||
|
|
prototype_single_Inf
|
||
|
|
DCD &7f800000
|
||
|
|
prototype_double_NaN
|
||
|
|
DCD &7ff00000,&00000001
|
||
|
|
prototype_single_NaN
|
||
|
|
DCD &7f800001
|
||
|
|
|
||
|
|
]
|
||
|
|
|
||
|
|
;------------------------------------------------------------------------------
|
||
|
|
|
||
|
|
[ :DEF: fpdata_s
|
||
|
|
|
||
|
|
AREA |.data|, DATA
|
||
|
|
|
||
|
|
EXPORT __fp_status_flags
|
||
|
|
__fp_status_flags
|
||
|
|
; default - all flags enabled.
|
||
|
|
DCD (&40:SHL:SysID_pos):OR:(((1:SHL:Except_len)-1):SHL:FPExceptE_pos)
|
||
|
|
|
||
|
|
EXPORT __fp_errblock
|
||
|
|
__fp_errblock
|
||
|
|
DCD 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0
|
||
|
|
|
||
|
|
EXPORT __rt_trap
|
||
|
|
__rt_trap
|
||
|
|
DCD 0
|
||
|
|
]
|
||
|
|
|
||
|
|
;==============================================================================
|
||
|
|
|
||
|
|
END
|