215 lines
7.0 KiB
NASM
215 lines
7.0 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; nans.s
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;
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; Copyright (C) Advanced RISC Machines Limited, 1994. All rights reserved.
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;
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; RCS Revision: 1
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; Checkin Date: 2007/06/29 02:59:16
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; Revising Author
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GET fpe.asm
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[ :DEF: thumb
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CODE32
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]
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AREA |.text|, CODE, READONLY
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EXPORT __fp_convert_NaNs
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EXPORT __fp_convert_NaN1
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EXPORT __fp_convert_NaN_1Of2
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EXPORT __fp_convert_NaN_2Of2
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__fp_convert_NaNs
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; First check for cases where the first operand determines which routine to
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; use - i.e. if it is a signalling NaN or not a NaN at all.
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ORRS Rtmp,OP1mlo,OP1mhi,LSL #1 ;First operand a NaN?
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BEQ __fp_convert_NaN_2Of2 ;If not, use ConvertNaN2Of2
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TST OP1mhi,#EIFracTop_bit ;First operand a sign.NaN?
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BEQ __fp_convert_NaN_1Of2 ;If so, use ConvertNaN1Of2
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; First operand is a quiet NaN. If second is a signalling NaN, we use
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; ConvertNaN2Of2; otherwise, we use ConvertNaN1Of2.
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ORRS Rtmp,OP2mlo,OP2mhi,LSL #1 ;Second operand a NaN?
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BEQ __fp_convert_NaN_1Of2 ;If not, use ConvertNaN1Of2
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TST OP2mhi,#EIFracTop_bit ;Second operand a sign.NaN?
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BNE __fp_convert_NaN_1Of2 ;If not, use ConvertNaN1Of2
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__fp_convert_NaN_2Of2
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CDebug3 4,"ConvertNaN2Of2: NaN =",OP2sue,OP2mhi,OP2mlo
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; We must check for an invalid operation trap *before* we start using shared
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; code, because the operands must be left unchanged for the trap handler.
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;; There is always a trap handler, and it doesn't care about the operands
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TST OP2mhi,#EIFracTop_bit ;Signalling NaN?
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BEQ ReturnIVO
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; Now we can transfer the NaN to OP1sue/mhi/mlo and use shared code.
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MOV OP1sue,OP2sue
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MOV OP1mhi,OP2mhi
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MOV OP1mlo,OP2mlo
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B ConvertNaN1_NoTrap
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__fp_convert_NaN1
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; We must check for an invalid operation trap *before* we start using shared
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; code, because the operands must be left unchanged for the trap handler.
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CDebug3 4,"ConvertNaN1: NaN =",OP1sue,OP1mhi,OP1mlo
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TST OP1mhi,#EIFracTop_bit ;Signalling NaN?
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BEQ ReturnIVO
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B ConvertNaN1_NoTrap ; becomes 0 = InvReas_SigNaN
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__fp_convert_NaN_1Of2
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CDebug3 4,"ConvertNaN1Of2: NaN =",OP1sue,OP1mhi,OP1mlo
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; We must check for an invalid operation trap *before* we start using shared
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; code, because the operands must be left unchanged for the trap handler.
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TST OP1mhi,#EIFracTop_bit ;Signalling NaN?
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BEQ ReturnIVO
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ConvertNaN1_NoTrap
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; Now we need to perform the actual NaN conversion. The rules here are:
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;
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; * The exponent field must be converted to the appropriate value for the
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; destination precision;
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;
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; * Fraction bits that are not used by the destination precision must be
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; cleared;
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;
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; * If result precision is single or double, units bit is forced to 1;
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;
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; * If the NE bit is 0 and we're converting to extended precision, the
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; bottom bit of the fraction must be set or cleared to indicate whether
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; the NaN is "really" single or double precision respectively.
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; Split according to result precision.
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TST Rins,#Single_mask
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BNE ConvertNaN1_ToSingle
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TST Rins,#Double_mask
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BNE ConvertNaN1_ToDouble
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;------------------------------------------------------------------------------
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ConvertNaN1_ToExtended
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; If NE=0, we just need to modify the exponent. Otherwise, we need to
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; establish the effective precision and set or clear the bottom bit of the
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; fraction appropriately.
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TST Rins,#NE_bit
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BNE ConvertNaN1_ToExtended_MantissaDone
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AND Rtmp,OP1sue,#ToExp_mask ;Isolate exponent field
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MOV Rtmp2,#NaNInfExp_Double:AND:&FF
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ORR Rtmp2,Rtmp2,#NaNInfExp_Double:AND:&FF00
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ASSERT NaNInfExp_Double <= &FFFF
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CMP Rtmp,Rtmp2 ;LO/EQ/HI if single/double/extended
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ASSERT NaNInfExp_Single < NaNInfExp_Double
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ASSERT NaNInfExp_Double < NaNInfExp_Extended
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BICLO OP1mlo,OP1mlo,#1 ;Bottom bit cleared for single NaN
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ORREQ OP1mlo,OP1mlo,#1 ;Bottom bit set for double NaN
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;Bottom bit unchanged for extended NaN
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ConvertNaN1_ToExtended_MantissaDone
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; Change exponent and return.
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AND OP1sue,OP1sue,#Sign_bit+Uncommon_bit
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ORR OP1sue,OP1sue,#NaNInfExp_Extended:AND:&FF
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ORR OP1sue,OP1sue,#NaNInfExp_Extended:AND:&FF00
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ASSERT NaNInfExp_Extended <= &FFFF
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TEQ OP1sue,OP1sue ;Force EQ condition
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IF Interworking :LOR: Thumbing
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BX LR
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ELSE
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MOV PC,LR
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ENDIF
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;------------------------------------------------------------------------------
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ConvertNaN1_ToDouble
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; Change exponent.
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AND OP1sue,OP1sue,#Sign_bit+Uncommon_bit
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ORR OP1sue,OP1sue,#NaNInfExp_Double:AND:&FF
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ORR OP1sue,OP1sue,#NaNInfExp_Double:AND:&FF00
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ASSERT NaNInfExp_Double <= &FFFF
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; Clear appropriate fraction bits and set the units bit. Note that we know
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; this won't change a NaN into an infinity unless someone is misusing
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; extended precision with NE=0.
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MOV OP1mlo,OP1mlo,LSR #11
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MOV OP1mlo,OP1mlo,LSL #11
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ORR OP1mhi,OP1mhi,#EIUnits_bit
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TEQ OP1sue,OP1sue ;Force EQ condition
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IF Interworking :LOR: Thumbing
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BX LR
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ELSE
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MOV PC,LR
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ENDIF
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;------------------------------------------------------------------------------
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ConvertNaN1_ToSingle
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; Change exponent.
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AND OP1sue,OP1sue,#Sign_bit+Uncommon_bit
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ORR OP1sue,OP1sue,#NaNInfExp_Single:AND:&FF
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ORR OP1sue,OP1sue,#NaNInfExp_Single:AND:&FF00
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ASSERT NaNInfExp_Single <= &FFFF
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; Clear appropriate fraction bits and set the units bit. Note that we know
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; this won't change a NaN into an infinity unless someone is misusing
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; extended precision with the NE bit equal to 0.
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MOV OP1mlo,#0
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BIC OP1mhi,OP1mhi,#&FF
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ORR OP1mhi,OP1mhi,#EIUnits_bit
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IF Interworking :LOR: Thumbing
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BX LR
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ELSE
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MOV PC,LR ;Note we still have EQ from above
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ENDIF
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;==============================================================================
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ReturnIVO
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; Return to the veneer with an IVO exception signalled.
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ORR OP1sue,OP1sue,#IVO_bits
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IF Interworking :LOR: Thumbing
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BX lr
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ELSE
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MOV pc, lr
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ENDIF
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;==============================================================================
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END
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