160 lines
6.3 KiB
NASM
160 lines
6.3 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; __stou64 single precision floating point to unsigned 64-bit integer convert
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;
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; Input: r0 - float to be converted
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; Output: r1 - most significant word of converted float in
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; unsigned 64-bit integer format
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; r0 - least significant word of converted float in
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; unsigned 64-bit integer format
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;
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; Local storage size and offsets
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LOC_SIZE EQU 0x18
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OrgOp1h EQU 0x14
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OrgOp1l EQU 0x10
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ExDResh EQU 0x0C
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ExDResl EQU 0x08
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NewResh EQU 0x14
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NewResl EQU 0x10
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GET fpe.asm
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GET kxarm.inc
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AREA |.text|, CODE, READONLY
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Export __stou64
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IMPORT FPE_Raise
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NESTED_ENTRY __stou64
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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MOVS r12, r0 ; Save original arg in case of exception
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MOVS r2, r0, ASR #SFrc_len ; Right justify exponent, save sign bit
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MOV r0, r0, LSL #SExp_len ; Left justify mantissa and
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ORR r1, r0, #1 << 31 ; insert hidden one (even for denorms)
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MOV r0, #0 ; clear low 32 bits of result
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BMI _ffix_negative ; If negative input, separate case
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RSBS r2, r2, #63 + SExp_bias ; Determine shift amount
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BLT shift_left ; Negative shift is a shift left,
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; NaN or INF; all are invalid op
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CMP r2, #64 ; See if shifting all bits out
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BGE shift_right_64 ; If shifting all bits out, return zero
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shift_right
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; r2 contains the right shift amount. It is on the range of 1..63.
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CMP r2, #32 ; Check if we are shifting >= 32
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SUBGE r2, r2, #32 ; If so, do a 32 bit shift by moving
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MOVGE r0, r1 ; words and adjusting the shift
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MOVGE r1, #0 ; amount
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RSB r2, r2, #32 ; 32 - right shift amount
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MOVS r3, r0, LSL r2 ; Check for inexact
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RSB r3, r2, #32 ; Right shift amount
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MOV r0, r0, LSR r3 ; Shift the result
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ORR r0, r0, r1, LSL r2 ; ..
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MOV r1, r1, LSR r3 ; ..
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MOVNE r3, #INX_bit ; If inexact, set inexact
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MOVEQ r3, #0 ; Otherwise set no exceptions
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B __stou64_return ; Return
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shift_left
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RSB r2, r2, #0 ; Get positive left shift amount
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MOV r3, #IVO_bit ; Set invalid
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MOV r1, r1, LSL r2 ; Shift result
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B __stou64_return ; Return
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shift_right_64 ; abs(Arg) < 1.0, so losing all bits
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MOV r0, #0 ; Return zero
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MOV r1, #0 ; Return zero
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MOVS r2, r12, LSL #1 ; Check for inexact
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MOVNE r3, #INX_bit ; If bits being lost, set inexact
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MOVEQ r3, #0
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B __stou64_return ; Return
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_ffix_negative
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AND r2, r2, #0xFF ; Mask off exponent field
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RSBS r2, r2, #63 + SExp_bias ; Determine shift amount
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BLE shift_left_neg ; Negative shift is a shift left, NaN
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; or INF
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CMP r2, #64 ; See if shifting all bits out
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BGE shift_right_64 ; If shifting all bits out, return zero
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shift_right_neg
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; r2 contains the right shift amount. It is on the range of 1..63.
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CMP r2, #32 ; Check if we are shifting >= 32
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SUBGE r2, r2, #32 ; If so, do a 32 bit shift by moving
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MOVGE r0, r1 ; words and adjusting the shift
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MOVGE r1, #0 ; amount
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RSB r2, r2, #32 ; 32 - right shift amount
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RSB r3, r2, #32 ; Right shift amount
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MOV r0, r0, LSR r3 ; Shift the result
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ORR r0, r0, r1, LSL r2 ; ..
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MOV r1, r1, LSR r3 ; ..
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RSBS r0, r0, #0 ; Negate result
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RSC r1, r1, #0 ; ..
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MOV r3, #IVO_bit ; Set invalid
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B __stou64_return ; Return
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shift_left_neg
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MOV r3, #IVO_bit ; Set invalid
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RSB r2, r2, #0 ; Get positive left shift amount
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MOV r1, r1, LSL r2 ; Shift result
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RSBS r0, r0, #0 ; Negate result
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RSC r1, r1, #0 ; ..
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B __stou64_return ; Return
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__stou64_return
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TST r3, #FPECause_mask ; Any exceptions?
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ADDEQ sp, sp, #LOC_SIZE ; If not, restore stack
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; and return
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; and return
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ENDIF
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STR r0, [sp, #ExDResl] ; Store default result
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STR r1, [sp, #ExDResh] ; ..
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ADD r0, sp, #NewResl ; Pointer to new result
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ORR r1, r3, #_FpSToU64 ; Exception information
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MOV r2, r12 ; Original arg
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CALL FPE_Raise ; Handle exception information
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ; Load new result
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LDR r1, [sp, #NewResh] ; ..
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ADD sp, sp, #LOC_SIZE ; Pop off exception record
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr} ; Return
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BX lr
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ELSE
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LDMFD sp!, {pc} ; Return
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ENDIF
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ENTRY_END __stou64
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END
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