90 lines
3.4 KiB
NASM
90 lines
3.4 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; Assembler source for FPA support code and emulator
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; ==================================================
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; Register allocations. Also used by "fplib".
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; Register usage at top level in undefined instruction handler.
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Rsp RN R13 ;Our stack pointer
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Rfp RN R12 ;Our "frame pointer" - points to ARM register dump
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Rins RN R11 ;Offending instruction itself
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Rwp RN R10 ;The workspace pointer/an entry sequence temporary
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Rtmp2 RN R9 ;A temporary
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Rtmp RN R8 ;A temporary
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; Register usage in the arithmetic and rounding routines, and the Prepare
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; and Round stage exception routines. Rfpsr, Rins, Rwp, Rfp and Rsp are
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; also part of this interface.
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OP1sue RN R1 ;The sign, uncommon bit and (sometimes) exponent of
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; the first or only operand
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OP1mhi RN R0 ;The mantissa of the first or only operand - high
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; word
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OP1mlo RN R2 ;The mantissa of the first or only operand - low
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; word
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RNDexp RN R3 ;The exponent of the number being rounded
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OP2sue RN R3 ;The sign, uncommon bit and (sometimes) exponent of
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; the second operand
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RNDdir RN R4 ;Direction number has already been rounded (0 = exact,
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; positive = rounded up, negative = rounded down)
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OP2mhi RN R5 ;The mantissa of the second operand - high word
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RNDprm RN R5 ;Precision and rounding mode for rounding, as two
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; adjacent 2 bit fields, lower one at position RM_pos
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; within word, higher one at RM_pos+2.
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OP2mlo RN R4 ;The mantissa of the second operand - low word
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Rarith RN R6 ;A temporary
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Rfpsr RN R7 ;FPSR contents
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; Two more temporaries, used when accessing ARM registers. The requirements
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; are (a) that they are not equal to any of the result registers (OP1sue,
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; OP1mhi, OP1mlo and Rarith); (b) that they are not equal to Rfpsr, Rins,
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; Rwp, Rfp or Rsp; (c) that they are not banked registers; (d) that they
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; are not equal to RNDprm.
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Rregno RN R3
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Rregval RN R4
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ASSERT Rregno <> OP1sue
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ASSERT Rregno <> OP1mhi
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ASSERT Rregno <> OP1mlo
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ASSERT Rregno <> Rfpsr
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ASSERT Rregno <> Rins
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ASSERT Rregno <> Rwp
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ASSERT Rregno <> Rfp
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ASSERT Rregno <> Rsp
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ASSERT Rregno < R8
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ASSERT Rregno <> RNDprm
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ASSERT Rregval <> OP1sue
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ASSERT Rregval <> OP1mhi
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ASSERT Rregval <> OP1mlo
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ASSERT Rregval <> Rfpsr
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ASSERT Rregval <> Rins
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ASSERT Rregval <> Rwp
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ASSERT Rregval <> Rfp
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ASSERT Rregval <> Rsp
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ASSERT Rregval < R8
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ASSERT Rregval <> RNDprm
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ASSERT Rregno <> Rregval
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; Some commonly used register lists:
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OP1regs RLIST {OP1mhi,OP1sue,OP1mlo}
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; ASSERT OP1sue < OP1mhi
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ASSERT OP1mhi < OP1mlo
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OP2regs RLIST {OP2sue,OP2mlo,OP2mhi}
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ASSERT OP2sue < OP2mhi
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; ASSERT OP2mhi < OP2mlo
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END
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