230 lines
8.2 KiB
C#
230 lines
8.2 KiB
C#
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// ----------------------------------------------------------------------------
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// ----------------------------------------------------------------------------
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using System;
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using System.Runtime.InteropServices;
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using System.Runtime.CompilerServices;
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using System.Threading;
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using Microsoft.Singularity.Isal;
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using Microsoft.Singularity.Hal;
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using Microsoft.Singularity.Io;
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#if ISA_IX
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using Microsoft.Singularity.Isal.IX;
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#endif
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namespace Microsoft.Singularity.Hal
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{
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//
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// Cpu contains per-CPU data structures that HAL sets up.
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//
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[AccessedByRuntime("referenced in c++")]
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[CLSCompliant(false)]
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[StructLayout(LayoutKind.Sequential, Pack=4)]
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public class Cpu
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{
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/////////////////////////////////////////////////////////////////////////////////////
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// Boot configuration information: this is all filled out by the loader or another CPU
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//////////////////////////////////////////////////////////////////////////////////
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public Cpu()
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{
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}
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protected Cpu(int id, UIntPtr stackLimit, UIntPtr stackBegin)
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{
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Size = 0;
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Id = id;
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KernelStackLimit = stackLimit;
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KernelStackBegin = stackBegin;
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}
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// Size of instance; this is a versioning/consistency check
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[AccessedByRuntime("referenced in c++")]
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public readonly int Size;
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// Cpu index
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[AccessedByRuntime("referenced in c++")]
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public readonly int Id;
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// The HAL is responsible for allocating a page for processor-specific
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// data structures. This is the address of that page. (Note it must be paragraph aligned.)
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[AccessedByRuntime("referenced in c++")]
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public readonly UIntPtr CpuRecordPage;
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// The HAL is responsible for allocating the kernel stack. The boundaries
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// are reported here.
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[AccessedByRuntime("referenced in c++")]
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public readonly UIntPtr KernelStackLimit; // lower bounds of stack
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[AccessedByRuntime("referenced in c++")]
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public readonly UIntPtr KernelStackBegin; // upper bounds of stack
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//Is 0 or 1...
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[AccessedByRuntime("referenced in c++")]
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public readonly int DomainBsp;
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///// NaticeCpu
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#if ISA_IX
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// This is our segment table.
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[AccessedByRuntime("referenced in c++")]
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DescriptorTable segments;
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#endif
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internal bool halted;
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///////////////////////////////////////////////////////////////////////
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// Kernel information: initialized by kernel during early boot
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///////////////////////////////////////////////////////////////////////
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// Low level initialization (no allocation allowed)
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[NoHeapAllocation]
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[AccessedByRuntime("referenced in c++")]
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public unsafe void Initialize()
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{
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if (DomainBsp == 0) {
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Platform.ThePlatform.RegisterCpu(this);
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}
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halted = false;
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}
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// High level intialization (requires object allocation)
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public void InitializeServices()
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{
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}
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// Called from the ISA Target upon interrupt dispatch.
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[NoHeapAllocation]
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public unsafe void DispatchInterrupt(InterruptContext *context)
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{
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Processor p = Processor.CurrentProcessor;
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int interrupt = context->ExceptionId;
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// Indicate that we are in an interrupt context.
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Thread target = null;
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Thread current = Processor.GetCurrentThread();
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Kernel.Waypoint(801);
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// Don't generate loads of output for debugger-related interrupts
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#if DEBUG_INTERRUPTS
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DebugStub.WriteLine("Int{0:x2}", __arglist(interrupt));
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context->Display();
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#endif
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if (Processor.IsSamplingEnabled) {
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if (p.nextSampleIdle == false) {
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p.Profiler.LogStackTrace(context->InstructionPointer,
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context->StackPointer);
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}
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p.nextSampleIdle = false;
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}
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if (halted) {
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p.clock.CpuResumeFromHaltEvent();
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halted = false;
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}
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unchecked {
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if (interrupt != p.clockInterrupt &&
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interrupt != p.timerInterrupt) {
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// We don't log the clockInterrupt because of all the spew.
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Tracing.Log(Tracing.Debug, "Interrupt 0x{0:x}, count={1:x}, eip={2:x} [CC={3:x8}]",
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(UIntPtr)(uint)interrupt,
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(UIntPtr)p.interruptCounts[interrupt],
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(UIntPtr)context->InstructionPointer,
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(UIntPtr)(uint)Processor.CycleCount);
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}
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}
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Monitoring.Log(Monitoring.Provider.Processor,
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(ushort)ProcessorEvent.Interrupt, 0,
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(uint)interrupt, 0, 0, 0, 0);
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if (interrupt == Kernel.HalIpiInterrupt) {
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#if DEBUG_IPI
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DebugStub.WriteLine("IPI received 0x{0:x2} on processor {1}",
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__arglist(interrupt, p.Id));
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#endif // DEBUG_DISPATCH_TIMER
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Platform.ClearFixedIPI(interrupt);
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//p.dispatcher.HandlePreemptionReschedule();
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}
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else if (interrupt == p.timerInterrupt) {
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// Polling on every timer interrupt is EXCEEDINGLY costly
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p.timer.ClearInterrupt();
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p.dispatcher.HandlePreemptionReschedule(p.timer);
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}
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else if (interrupt == p.clockInterrupt) {
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p.clock.ClearInterrupt();
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#if DEBUG
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// Check for a debug break.
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if (DebugStub.PollForBreak()) {
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DebugStub.WriteLine("Debugger ctrl-break after interrupt 0x{0:x2}",
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__arglist(interrupt));
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DebugStub.Break();
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}
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#endif // DEBUG
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}
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#if ISA_IX
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else if (interrupt == EVectors.GCSynchronization) {
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Platform.ClearFixedIPI(interrupt);
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MpExecution.GCSynchronizationInterrupt();
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}
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else if (interrupt == EVectors.SpuriousInterrupt) {
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// FIXME: identify the source of these isolated interrupts after the
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// warmboot. Ignore them for now.
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DebugStub.WriteLine("Spurious interrupt");
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}
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#endif // ISA_IX
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else {
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if (!Platform.InternalInterrupt((byte)interrupt)) {
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HalPic pic = p.GetPic();
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DebugStub.Assert(pic != null);
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pic.ClearInterrupt((byte)interrupt);
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IoIrq.SignalInterrupt(pic.InterruptToIrq((byte)interrupt));
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#if DEBUG_DISPATCH_IO
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DebugStub.WriteLine("++DispatchInterruptEvent Irq={0:x2}, Thread={1:x8}",
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__arglist(pic.InterruptToIrq((byte)interrupt),
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Kernel.AddressOf(target)));
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#endif // DEBUG_DISPATCH_IO
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p.dispatcher.HandleIOReschedule();
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}
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else {
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// Potentially missed interrupt
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DebugStub.Break();
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}
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}
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#if DEBUG_INTERRUPTS
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DebugStub.WriteLine("(2nd)Int{0:x2}", __arglist(interrupt));
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context->Display();
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if (!Processor.InterruptsDisabled()) {
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DebugStub.WriteLine(" interrupts enabled!!!!!!!");
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DebugStub.Break();
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}
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#if DEBUG_DEEPER
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DebugStub.WriteLine("Int{0:x2}", __arglist(interrupt));
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Thread.DisplayAbbrev(ref context, " int end");
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#endif
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#endif
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// Now swap in the resulting current thread. (Note that this call will not return.)
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Isa.GetCurrentThread()->spill.Resume();
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}
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}
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}
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