179 lines
7.7 KiB
NASM
179 lines
7.7 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains x86-specific assembly code related to context save and restore.
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;;; The key goal here is to keep this set of code as small as possible, in favor
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;;; of portable C++ or C# code.
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CODE32
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AREA |.text|, CODE, ARM
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|defining ?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SA_NPAU1@@Z| EQU 1
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|defining ?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SA_NPAU1@PAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z| EQU 1
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|defining ?m_Resume@Struct_Microsoft_Singularity_Isal_SpillContext@@SAXPAU1@@Z| EQU 1
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|defining ?g_ResetCurrent@Struct_Microsoft_Singularity_Isal_SpillContext@@SAXXZ| EQU 1
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include hal.inc
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;;; Save takes one argument - a context record to save the context in. It saves all the
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;;; nonvolatile state (it does not bother saving caller save regs.)
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;;;
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;;; This function returns true after saving the context. When the context is resumed, control
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;;; resumption will occur at the point this function returned, but with a false
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;;; return value.
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;;;
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;;; Calling conventions are normal __fastcall.
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;; __fastcall bool SaveContext(Context *context)
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LEAF_ENTRY ?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SA_NPAU1@@Z
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;; Save the bulk of the registers (r0-r12).
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stmia r0, {r0-r12}
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;; Save sp and (stale) lr.
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str sp, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___sp]
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str lr, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___lr]
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;; Save lr as the pc.
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str lr, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___pc]
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;; Save cpsr
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mrs r1, cpsr
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str r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___cpsr]
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;; Overright r0, so the return value contains zero on context resume
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ldr r1, =0
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str r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r0]
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;; Save stack limit
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GET_THREAD_FIELD_ADDR r2, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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ldr r2, [r2]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___stackLimit]
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;; Set spilled flag
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ldr r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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orr r2, r2, #Struct_Microsoft_Singularity_Isal_SpillContext_ContentsSpilled
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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;; return true for initial save
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ldr r0, =1
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bx lr
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LEAF_END
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;;; Save takes two arguments - a context record to save the context in, and
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;;; an interrupt frame to describe an interruption location.
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;;;
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;;; Calling conventions are normal __fastcall.
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;; __fastcall bool SaveContext(Context *context, InterruptContext *interrupt)
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LEAF_ENTRY ?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SA_NPAU1@PAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z
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;; Pick up registers from the interrupt context
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___r0]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r0]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___r1]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r1]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___r2]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r2]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___r3]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r3]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___r12]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r12]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___lr]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___lr]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___sp]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___sp]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___pc]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___pc]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___cpsr]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___cpsr]
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ldr r2, [r1, #Struct_Microsoft_Singularity_Isal_InterruptContext___instruction]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___instruction]
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;; Save the rest of the registers from the current state
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add r2, r0, #Struct_Microsoft_Singularity_Isal_SpillContext___r4
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stmia r2, {r4-r11}
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;; Save stack limit
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GET_THREAD_FIELD_ADDR r2, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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ldr r2, [r2]
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___stackLimit]
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;; Set spilled flag
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ldr r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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orr r2, r2, #Struct_Microsoft_Singularity_Isal_SpillContext_ContentsSpilled
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str r2, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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;; We're done
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bx lr
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LEAF_END
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;;; Resume restores the processor state to the state described in the given
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;;; context record.
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;;;
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;;; __fastcall void ResumeContext(Struct_Microsoft_Singularity_Isal_SpillContext *context);
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|?m_Resume@Struct_Microsoft_Singularity_Isal_SpillContext@@SAXPAU1@@Z| PROC
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;; Switch to supervisor mode so we can get an atomic resume including CPSR.
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mrs r1, cpsr
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bic r1, r1, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Mask
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orr r1, r1, #Struct_Microsoft_Singularity_Isal_Arm_ProcessorMode_Supervisor
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msr cpsr_c, r1
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;; Clear spilled flag.
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ldr r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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bic r1, r1, #Struct_Microsoft_Singularity_Isal_SpillContext_ContentsSpilled
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str r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___spillFlags]
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;; Restore stack limit.
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ldr r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___stackLimit]
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GET_THREAD_FIELD_ADDR r2, r12, #Struct_Microsoft_Singularity_Isal_ThreadRecord___activeStackLimit
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str r1, [r2]
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;; Move saved CPSR into SPSR.
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ldr r1, [r0, #Struct_Microsoft_Singularity_Isal_SpillContext___cpsr]
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msr spsr, r1
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;; Restore banked pre-interrupt registers (use R3 as pointer to banked registers).
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add r3, r0, #Struct_Microsoft_Singularity_Isal_SpillContext___sp
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ldmia r3, {sp,lr}^
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;; Resume unbanked pre-interrupt state.
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ldmia r0, {r0-r12,pc}^
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ENDP
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;;; ResetContext resets the current context fp & debug register state to a canonical state
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;;; for interrupt handler code. This should only be used after saving the current context.
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;;;
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;;; Calling conventions are normal __fastcall.
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;;;
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;;; __fastcall void ResetCurrent();
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LEAF_ENTRY ?g_ResetCurrent@Struct_Microsoft_Singularity_Isal_SpillContext@@SAXXZ
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bx lr
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LEAF_END
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END
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