263 lines
11 KiB
NASM
263 lines
11 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains x86-specific assembly code handling dispatching of interrupts.
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include hal.inc
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;;; IdtDispatchers are the dispatch functions used for populating the Idt. Each one
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;;; pushes its interrupt id, along with a dummy error code if necessary to normalize
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;;; the stack, and jumps to the central dispatch routine
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DISPATCH_CLEAN MACRO num
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align SIZEOF Struct_Microsoft_Singularity_Isal_IX_InterruptTable_Dispatcher
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push 0 ; No error
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push num
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jmp SYMFIX(?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ)
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ENDM
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DISPATCH_ERR MACRO num
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align SIZEOF Struct_Microsoft_Singularity_Isal_IX_InterruptTable_Dispatcher
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push num
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jmp SYMFIX(?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ)
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ENDM
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_IdtDispatchers proc
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DISPATCH_CLEAN 000h ; #DE Divide-by-Zero
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DISPATCH_CLEAN 001h ; #DB Debug Exception
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DISPATCH_CLEAN 002h ; NMI Non-Maskable-Interrupt
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DISPATCH_CLEAN 003h ; #BP Breakpoint
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DISPATCH_CLEAN 004h ; #OF OVerflow
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DISPATCH_CLEAN 005h ; #BR Bound-Range
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DISPATCH_CLEAN 006h ; #UD Invalid Opcode
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DISPATCH_CLEAN 007h ; #NM Device Not Available
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DISPATCH_ERR 008h ; #DF Double Fault
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DISPATCH_CLEAN 009h ; Unused (was x87 segment except)
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DISPATCH_ERR 00ah ; #TS Invalid TSS
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DISPATCH_ERR 00bh ; #NP Sgement Not Present
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DISPATCH_ERR 00ch ; #SS Stack Exception
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DISPATCH_ERR 00dh ; #GP General Protection
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DISPATCH_ERR 00eh ; #PF Page Fault
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DISPATCH_CLEAN 00fh ; Reserved
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DISPATCH_CLEAN 010h ; #MF x87 Math Error
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DISPATCH_ERR 011h ; #AC Alignment Check
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DISPATCH_CLEAN 012h ; #MC Machine Check
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DISPATCH_CLEAN 013h ; #XF SIMD Exception
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DISPATCH_CLEAN 014h ; 014h exception
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DISPATCH_CLEAN 015h ; 015h exception
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DISPATCH_CLEAN 016h ; 016h exception
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DISPATCH_CLEAN 017h ; 017h exception
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DISPATCH_CLEAN 018h ; 018h exception
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DISPATCH_CLEAN 019h ; 019h exception
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DISPATCH_CLEAN 01ah ; 01ah exception
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DISPATCH_CLEAN 01bh ; 01bh exception
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DISPATCH_CLEAN 01ch ; 01ch exception
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DISPATCH_CLEAN 01dh ; 01dh exception
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DISPATCH_CLEAN 01eh ; 01eh exception
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DISPATCH_CLEAN 01fh ; 01fh exception
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DISPATCH_CLEAN 020h ; 021h: first interrupt
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_num = 021h ; 021h to 0ffh
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WHILE _num LE 0ffh
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DISPATCH_CLEAN _num
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_num = _num + 1
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ENDM
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_IdtDispatchers endp
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;;; GetDispatchers returns the address of the IdtDispatchers array. This
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;;; is necessary since we can't directly take the address of a function in managed code.
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SYMFIX(?g_GetDispatchers@Struct_Microsoft_Singularity_Isal_IX_InterruptTable@@SIPAUStruct_Microsoft_Singularity_Isal_IX_InterruptTable_Dispatcher@@XZ) proc
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lea eax, _IdtDispatchers
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ret
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SYMFIX(?g_GetDispatchers@Struct_Microsoft_Singularity_Isal_IX_InterruptTable@@SIPAUStruct_Microsoft_Singularity_Isal_IX_InterruptTable_Dispatcher@@XZ) endp
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;;; LoadDispatchTable should be called on each processor to initialize its idt register to the
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;;; shared dispatch table.
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SYMFIX(?g_LoadIdt@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ) proc
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lidt fword ptr _Idtr
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ret
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SYMFIX(?g_LoadIdt@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ) endp
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;;; DispatchVector implements the meat of the low level interrupt dispatching logic. Its goal
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;;; is to implement the transition to high level code with minimal overhead.
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;;;
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;;; There are essentially two tasks: save the context (if appropriate), and switch to the
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;;; interrupt processing stack.
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;;;
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;;; This function either returns via iretd, or else doesn't return at all (because the
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;;; handler called RestoreContext.)
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;;;
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;;; On entry to DispatchVector, the stack looks like this:
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;;;
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;;; [TOP] (after pushing regs)
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;;; interrupt vector [esp] [esp+3P]
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;;; interrupt err (parameter) [esp+1P] [esp+4P]
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;;; interrupted eip [esp+2P] [esp+5P]
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;;; interrupted cs [esp+3P] [esp+6P]
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;;; interrupted efl [esp+4P] [esp+7P]
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;;; [PAGING/X64]
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;;; interrupted esp [esp+5P] [esp+8P]
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;;; interrupted ss [esp+6P] [esp+9P]
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;;; [NON-PAGING]
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;;; previous stack continues esp+5P esp+8P
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;;;
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SYMFIX(?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ) proc
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ifdef PAGING
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if ISA_IX86
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;; Fix up segment ds, es to point to valid values
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push ss
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pop ds
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push ss
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pop es
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endif
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;; If we've arrived from ring 3 FS will be invalid.
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push Struct_Microsoft_Singularity_Isal_IX_DescriptorTable_Gdt._pp - Struct_Microsoft_Singularity_Isal_IX_DescriptorTable_Gdt._nul
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pop fs
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endif
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;; Save regs in InterruptContext
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push PAX
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push PCX
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push PDX
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ifdef ISA_IX64
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push r8
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push r9
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push r10
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push r11
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endif
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;; Decide if/where to stash the context. For now, we use hard-coded
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;; constants based on the vector to make the decision. Eventually this could be
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;; delegated to the HAL for more dynamic control of behaviors.
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;; The lowest vectors are exceptions - context save into ProcessorRecord, where the
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;; cpu state will be visible to the debugger infrastructure.
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mov PDX, [PSP].Struct_Microsoft_Singularity_Isal_InterruptContext._vector
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cmp PDX, Struct_Microsoft_Singularity_Isal_InterruptContext_VectorExceptionMax
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jg not_exception
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GET_PROCESSOR_CONTEXT PAX
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lea PCX, [PAX].Struct_Microsoft_Singularity_Isal_CpuRecord._spill
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jmp save_context
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not_exception:
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;; The middle vectors are fast interrupts - no context save. These interrupts may
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;; be used for fast operations which do not interact with the scheduler; control will
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;; always resume at the interrupted location.
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cmp PDX, Struct_Microsoft_Singularity_Isal_InterruptContext_VectorSchedulerMin
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jl skip_save
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;; The highest vectors are normal interrupts - context save into ThreadRecord. Typically
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;; control may be resumed on a different thread.
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GET_THREAD_CONTEXT PAX
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lea PCX, [PAX].Struct_Microsoft_Singularity_Isal_ThreadRecord._spill
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save_context:
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;; Note PCX has the context buffer from above
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mov PDX, PSP
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call SYMFIX(?m_Save@Struct_Microsoft_Singularity_Isal_SpillContext@@SI_NPAU1@PAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z)
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skip_save:
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;; Save previous stack limit
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GET_THREAD_RECORD_FIELD PCX, _activeStackLimit
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push PCX
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;; See if we are on the interrupt stack
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GET_CPU_RECORD_FIELD PDX, _interruptStackLimit
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cmp PDX, PCX
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mov PCX, PSP ; stash old stack ptr; doesn't change flags
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je no_switch
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;; switch to interrupt stack
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GET_CPU_RECORD_FIELD PAX, _interruptStackBegin
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mov PSP, PAX
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SET_THREAD_RECORD_FIELD _activeStackLimit, PDX
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no_switch:
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;; Save the old stack pointer
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push PCX
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;; InterruptContext is old PSP + 4
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add PCX, SIZEOF PWORD
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;; call the handler
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call SYMFIX(?g_DispatchInterrupt@Class_Microsoft_Singularity_Isal_Isa@@SIXPAUStruct_Microsoft_Singularity_Isal_InterruptContext@@@Z)
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;; Note that we may or may not get here, depending on whether the InterruptDispatch routine
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;; returned or not (it may have restored a previous context.) If we did get here, return
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;; back to the interrupted context.
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;; Restore the old stack pointer and limit
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pop PSP
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pop PAX
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SET_THREAD_RECORD_FIELD _activeStackLimit, PAX
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;; Restore caller save regs, do normal interrupt resume
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ifdef ISA_IX64
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pop r11
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pop r10
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pop r9
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pop r8
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endif
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pop PDX
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pop PCX
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pop PAX
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;; Discard vector/err
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add PSP, SIZEOF PWORD * 2
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;; Return
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jmp [SYMFIX(?c_returnFromInterrupt@Class_Microsoft_Singularity_Isal_Isa@@2PAUvoid@@A)]
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SYMFIX(?g_DispatchVector@Class_Microsoft_Singularity_Isal_Isa@@SIXXZ) endp
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.data
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;;; We have to manually declare this variable to get it properly aligned. This seems to be a bartok bug.
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align 16
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?c_idt@Class_Microsoft_Singularity_Isal_Isa@@2?AUStruct_Microsoft_Singularity_Isal_IX_InterruptTable@@A Struct_Microsoft_Singularity_Isal_IX_InterruptTable { }
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;;; _Idtr is a global structure which is suitable for passing to the lidt instruction.
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IDTR struct 2
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_limit UINT16 ?
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_base PWORD ?
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IDTR ends
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align 16
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;; We want to align the PWORD after the offset, so add padding here.
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dw ?
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ifdef ISA_IX64
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dw ?
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dw ?
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endif
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_Idtr IDTR { \
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(SIZEOF Struct_Microsoft_Singularity_Isal_IX_InterruptTable) - 1, \
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?c_idt@Class_Microsoft_Singularity_Isal_Isa@@2?AUStruct_Microsoft_Singularity_Isal_IX_InterruptTable@@A }
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END
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