365 lines
14 KiB
C#
365 lines
14 KiB
C#
////////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: BusMasterDma.cs
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//
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// See "Programming Interface for Bus Master IDE Controller"
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// or www.t13.org 1510D Draft "ATA/ATAPI Host Adapters Standard(ATA - Adapter)"
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//
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// 1. Software prepares a PRD Table in host memory.
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// 2. Software provides the starting address of the PRD Table by loading the PRD Table
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// Pointer Register.
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// Setting of the Read/Write Control bit specifies the direction of the data transfer.
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// Clearing the Interrupt and Error bits in the ATA Bus Master Status register
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// to zero readies the adapter for a data transfer.
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// 3. Software issues the appropriate DMA transfer command to the device.
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// 4. Software initiates the bus master function by writing a one to the Start bit
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// in the ATA Bus Master Command Register for the appropriate channel.
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// 5. The adapter transfers data to/from host memory responding to DMA requests from the ATA device.`
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//
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//#define DEBUG_BUS_MASTER_DMA
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using System;
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using System.Text;
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using System.Threading;
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using System.Runtime.CompilerServices; //StructAlign attribute
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using System.Runtime.InteropServices; //structLayout attribute
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using Microsoft.SingSharp;
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using Microsoft.Singularity;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Drivers.IDE;
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using Microsoft.Singularity.V1.Services;
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namespace Microsoft.Singularity.Drivers.IDE
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{
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[CLSCompliant(false)]
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public class BusMasterDma
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{
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enum BmState
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{
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BmIdle = 0,
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BmPrepared ,
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BmArmed,
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BmDisarmed,
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}
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public const int PRD_BYTES_PER_ENTRY = 8;
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public const int PRD_ALIGNMENT = 4096;
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public const int PRD_MAX_ENTRIES = 4096 / PRD_BYTES_PER_ENTRY;
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// BusMaster Status Bits
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private const byte BUSMASTER_STATUS_MASK_DEVICE1_DMA_OK = 0x40;
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private const byte BUSMASTER_STATUS_MASK_DEVICE0_DMA_OK = 0x20;
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private const byte BUSMASTER_STATUS_MASK_INTERRUPT = 0x04;
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private const byte BUSMASTER_STATUS_MASK_ERROR = 0x02;
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private const byte BUSMASTER_STATUS_MASK_ACTIVE = 0x01;
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//BusMaster Control bits
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private const byte BUSMASTER_CONTROL_MASK_WRITE = 0x08;
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private const byte BUSMASTER_CONTROL_MASK_START = 0x01;
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private const byte BUSMASTER_CONTROL_MASK_STOP = 0x00;
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private IoPort commandPort;
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private IoPort statusPort;
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private IoPort prdPort;
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private IoMemory prdRegion;
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private IdeConfig ideConfigHandle;
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private bool runningVPC;
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private BmState busMasterState; // the state we think the BusMaster it is in
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const byte PrdTableTerminate = 0x80;
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public BusMasterDma(IdeConfig! ideConfig)
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{
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ideConfigHandle = ideConfig;
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// Set up BusMaster ports for this controller
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// <command, status, PRD table>
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commandPort = ideConfig.DmaBase.PortAtOffset(0, 1, Access.ReadWrite);
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statusPort = ideConfig.DmaBase.PortAtOffset(2, 1, Access.ReadWrite);
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prdPort = ideConfig.DmaBase.PortAtOffset(4, 4, Access.ReadWrite);
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// PRD needs to be 4-byte aligned and within one 4k page.
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prdRegion =
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IoMemory.AllocatePhysical(PRD_MAX_ENTRIES * PRD_BYTES_PER_ENTRY,
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PRD_ALIGNMENT);
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} // BusMasterInitialize
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public void Uninitialize ()
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{
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commandPort = null; //???
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}
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public void Setup ()
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{
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}
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public void BmPrepareController (IdeRequest! ideRequest)
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{
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// Perform steps 1 and 2 above: set up PRD, clear
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// error snd interrupt
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// Init. Scatter Gather List Register
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uint thePrd = FillPrdTable(ideRequest);
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prdPort.Write32(thePrd);
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// Clear Errors
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byte status = (byte) (BUSMASTER_STATUS_MASK_INTERRUPT | BUSMASTER_STATUS_MASK_ERROR);
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statusPort.Write8(status);
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return;
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} // BmPrepareController
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public void SetVirtualized()
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{
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runningVPC = true;
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return;
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}
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public int Arm (IdeRequest! ideRequest)
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{
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byte value = BUSMASTER_CONTROL_MASK_START;
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if (ideRequest.Command == IdeCmdType.Read) {
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value |= BUSMASTER_CONTROL_MASK_WRITE;
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}
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commandPort.Write8(value); // enable BM
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return 0;
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} // BmArm
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public byte GetStatus()
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{
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byte status = statusPort.Read8();
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return status;
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}
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public bool InterruptHigh()
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{
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//probe the status register to see if we have been interrupted
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byte status = statusPort.Read8();
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if ((status & (byte) BUSMASTER_STATUS_MASK_INTERRUPT) == 0) {
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return false;
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}
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return true;
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}
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public void Disarm ()
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{
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//According to the "Programming Interface for Bus Master IDE Controller"
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// 1) reset the Start/Stop bit in command register
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// 2) read controller status
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// 3) read drive status
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// to determine if the xfer completed successfully.
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commandPort.Write8(BUSMASTER_CONTROL_MASK_STOP); // disable BM
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//Tracing.Log(Tracing.Debug," stop: fullstatus ={0:x}\n",(UIntPtr)ideConfigHandle.IdeController.ReadFullStatus());
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byte status = GetStatus();
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if ((status & (byte)BUSMASTER_STATUS_MASK_INTERRUPT) == 0) {
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Tracing.Log(Tracing.Debug,"BusMaster.Disarm: interrupt line not set {0}!\n",(UIntPtr) status);
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DebugStub.WriteLine("BusMaster.Disarm: interrupt line not set {0}!\n",__arglist(status));
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//DebugStub.Break();
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}
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if ((status & (byte)BUSMASTER_STATUS_MASK_ERROR) > 0) {
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Tracing.Log(Tracing.Debug,"BusMaster.Disarm: error!!!!\n",(UIntPtr) status);
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DebugStub.WriteLine("BusMaster.Disarm: error!!!!\n",__arglist(status));
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//DebugStub.Break();
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}
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status = (byte) (BUSMASTER_STATUS_MASK_INTERRUPT | BUSMASTER_STATUS_MASK_ERROR);
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statusPort.Write8( status); // clear interrupt BM
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//Tracing.Log(Tracing.Debug,"cntlr status ={0:x}\n",(UIntPtr)ideConfigHandle.IdeController.ReadFullStatus());
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//Tracing.Log(Tracing.Debug,"bm status : {0:x}",(UIntPtr) statusPort.Read8());
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} // BmDisarm
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[ System.Diagnostics.Conditional("DEBUG_BUS_MASTER_DMA") ]
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public void DumpPrd()
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{
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for (int i = 0; i < PRD_MAX_ENTRIES; i++) {
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uint address;
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uint length;
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bool eot;
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ReadPrdEntry(i, out address, out length, out eot);
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Tracing.Log(Tracing.Debug,
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"prd[{0}]: {1:x8} {2:x4}\n",
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(UIntPtr) i,
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(UIntPtr) address,
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(UIntPtr) length);
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if (eot) {
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Tracing.Log(Tracing.Debug, "prd[{0}]: EOT\n", (UIntPtr) i);
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break;
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}
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}
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}
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private uint FillPrdTable(IdeRequest! ideRequest)
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{
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// given a memory address and a length generate
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// a Physical Region Descriptor Table (PDRT) to be used
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// in a IDE busmaster DMA transfer
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//a PRDT table is an array of PRD entries, each 8 bytes in
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//length. There is no count associated with this structure
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// Bit 7 of the last byte of the last entry signifies the
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//end of the table
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// PRD (Physical Region Descriptor)
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// the first 4 bytes of a PRD specify the memory address
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// Bytes 5 and 6 (16 bits) specify the length.
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// At most a PRD can specify a transfer of 64KB.
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// The memory specified by a PRD cannot cross a 64KB boundary
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// Any transfer that would cross such a boundary needs to be
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// split into to separate PRDs
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uint addr = (uint)((UIntPtr)ideRequest.BufferAddress + ideRequest.BufferOffset);
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uint len = (uint)ideRequest.Length;
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// Write a bad entry at the end
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WritePrdEntry(PRD_MAX_ENTRIES - 1, 0, 0xbad1, true);
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uint baseAddr = addr;
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uint bytesToMap = len;
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int i = 0;
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while (0 != bytesToMap) {
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uint did = WritePrdChunk(i, baseAddr, bytesToMap);
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baseAddr += did;
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bytesToMap -= did;
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i++;
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}
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// DEBUG CHECK
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uint computedLen = 0 ;
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bool eotFound = false;
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for (i = 0; i < PRD_MAX_ENTRIES; i++) {
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uint dummy;
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uint length;
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bool eot;
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ReadPrdEntry(i, out dummy, out length, out eot);
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computedLen = computedLen + length;
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if (eot) {
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eotFound = true;
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break;
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}
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}
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if (computedLen != len || !eotFound) {
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throw new ApplicationException("PRD length mismatch");
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}
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DumpPrd();
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return (uint) prdRegion.PhysicalAddress.Value;
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}
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private UIntPtr Get64KLimit(UIntPtr a)
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{
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const uint count = 0x10000;
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return (a.ToUInt32() + count) & ~(count - 1u);
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}
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// Write a descriptor for up to 64K of user data. Write stops on
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// 64K boundaries or discontinuity in physical memory.
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//
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// Returns the number of bytes written into PRD.
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private uint WritePrdChunk(int prdIndex,
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UIntPtr baseVA,
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uint baseVALength)
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{
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UIntPtr basePA;
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UIntPtr bytesOnPage;
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if (!DeviceService.GetDmaPhysicalAddress(baseVA,
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out basePA,
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out bytesOnPage)) {
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throw new ApplicationException(
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"Bad physical address translation"
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);
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}
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UIntPtr basePALimit = Get64KLimit(basePA);
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if (basePALimit > basePA + baseVALength) {
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basePALimit = basePA + baseVALength;
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}
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UIntPtr expectedPA = basePA + bytesOnPage;
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baseVA += bytesOnPage;
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while (expectedPA < basePALimit) {
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UIntPtr currentPA;
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if (!DeviceService.GetDmaPhysicalAddress(baseVA,
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out currentPA,
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out bytesOnPage)) {
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throw new ApplicationException(
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"Bad physical address translation"
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);
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}
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if (currentPA != expectedPA) {
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// Physical page discontinuity
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break;
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}
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expectedPA = currentPA + bytesOnPage;
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baseVA = baseVA + bytesOnPage;
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}
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if (expectedPA < basePALimit) {
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basePALimit = expectedPA;
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}
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uint done = (basePALimit - basePA).ToUInt32();
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WritePrdEntry(prdIndex,
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basePA.ToUInt32(),
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(ushort) (done & 0xffff),
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done == baseVALength);
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return done;
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}
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private void
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WritePrdEntry(int index,
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uint addr,
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uint length,
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bool endOfTable)
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requires length != 0 && length <= 0x10000;
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{
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// PRD structure in octets:
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// - 0:3 baseAddress
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// - 4:5 length
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// - 6:6 reserved
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// - 7:7 end of table
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int baseOffset = index * PRD_BYTES_PER_ENTRY;
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this.prdRegion.Write32(baseOffset,
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ByteOrder.HostToLittleEndian(addr));
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ushort slen = (ushort)(length & 0xffffu); // 0 == 64K
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this.prdRegion.Write16(baseOffset + 4,
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ByteOrder.HostToLittleEndian(slen));
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this.prdRegion.Write8(baseOffset + 7,
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endOfTable ? PrdTableTerminate : (byte)0);
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}
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private void
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ReadPrdEntry(int index,
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out uint addr,
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out uint length,
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out bool endOfTable)
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{
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int baseOffset = index * PRD_BYTES_PER_ENTRY;
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addr = ByteOrder.LittleEndianToHost(
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this.prdRegion.Read32(baseOffset)
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);
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ushort slen = ByteOrder.LittleEndianToHost(
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this.prdRegion.Read16(baseOffset + 4)
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);
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length = (slen == 0) ? 0x10000u : (uint)slen;
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byte end = this.prdRegion.Read8(baseOffset + 7);
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endOfTable = (end == PrdTableTerminate);
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}
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} // BusMaster Class
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}//namespace
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