208 lines
8.6 KiB
NASM
208 lines
8.6 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; __dtoi64 double precision floating point to signed 64-bit integer convert
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;
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; Input: r1 - Most significant word of the double to be converted
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; r0 - Least significant word of the double to be converted
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;
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; Output: r1 - Most significant word of the converted double in signed
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; 64-bit integer format
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; r0 - Least significant word of the converted double in signed
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; 64-bit integer format
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;
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; Local storage size and offsets
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LOC_SIZE EQU 0x18
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OrgOp1h EQU 0x14
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OrgOp1l EQU 0x10
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ExDResh EQU 0x0C
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ExDResl EQU 0x08
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NewResh EQU 0x14
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NewResl EQU 0x10
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GET fpe.asm
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GET kxarm.inc
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AREA |.text|, CODE, READONLY
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Export __dtoi64
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IMPORT FPE_Raise
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NESTED_ENTRY __dtoi64
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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STR r1, [sp, #OrgOp1h] ; Save off original args in case of exception
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ORRS r12, r0, r1, LSL #1 ; Check for zero
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STR r0, [sp, #OrgOp1l] ; ..
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MOVEQ r1, r0 ; return if zero (r0 already zero)
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ADDEQ sp, sp, #LOC_SIZE ; restore stack
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; ..
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; ..
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ENDIF
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MOVS r2, r1, LSL #1 ; Right justify exponent, save sign bit in C
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MOV r1, r1, LSL #11 ; Left justify mantissa
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ORR r1, r1, r0, LSR #21 ; ..
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; ..
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MOV r0, r0, LSL #11 ; ..
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ORR r1, r1, #1 << 31 ; Insert hidden one (even for denorms)
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BCS _ffix_negative ; If negative input, separate case
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MOV r3, #DExp_bias+1 ; r3 = 63 + DExp_bias
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ADD r3, r3, #62 ; ..
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SUBS r2, r3, r2, LSR #21 ; Determine shift amount
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BLE shift_left ; Negative shift is a shift left, NaN,
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; or INF
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CMP r2, #64 ; See if shifting all bits out
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BGE shift_right_64 ; If shifting all bits out, return zero
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shift_right
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MOV r12, #0 ; Need to clear r12 for inexact check
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CMP r2, #32 ; See if shift amount >= 32
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BLT shift_right_31 ; If not, shift right 31 or less
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MOV r12, r0 ; If >= 32, save lost bits in temp reg,
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MOV r0, r1 ; shift by moving words, and
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MOV r1, #0 ; adjust the shift amount
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SUB r2, r2, #32 ; ..
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shift_right_31
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RSB r3, r2, #32 ; Check for inexact
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ORRS r12, r12, r0, LSL r3 ; ..
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MOV r0, r0, LSR r2 ; Shift the result
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ORR r0, r0, r1, LSL r3 ; ..
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MOV r1, r1, LSR r2 ; ..
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MOVNE r3, #INX_bit ; Set inexact if inexact
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MOVEQ r3, #0 ; Otherwise set to no exceptions
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B __dtoi64_return ; Return
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shift_left
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RSB r2, r2, #0 ; Get left shift amount
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CMP r2, #32 ; If >= 32, shift by moving words, and
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MOVGE r1, r0 ; adjusting shift amount
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MOVGE r0, #0 ; ..
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SUBGE r2, r2, #32 ; ..
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MOV r1, r1, LSL r2 ; Perform rest of shift
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RSB r3, r2, #32 ; ..
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ORR r1, r1, r0, LSR r3 ; ..
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MOV r0, r0, LSL r2 ; ..
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MOV r3, #IVO_bit ; Overflow so set invalid operation
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B __dtoi64_return ; Return
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shift_right_64 ; 0.0 < abs(Arg) < 1.0, so losing all bits
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MOV r3, #INX_bit ; Set inexact
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MOV r0, #0 ; Return zero
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MOV r1, #0 ; ..
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B __dtoi64_return ; Return
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_ffix_negative
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MOV r3, #DExp_bias+1 ; r3 = 63 + DExp_bias
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ADD r3, r3, #62 ; ..
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SUBS r2, r3, r2, LSR #21 ; Determine shift amount
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BLT shift_left_neg ; Negative shift is a shift left, NaN,
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; or INF
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BEQ special_int64_min ; Special case of 0x8000000000000000
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CMP r2, #64 ; See if shifting all bits out
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BGE shift_right_64 ; If shifting all bits out, return zero
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shift_right_neg
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MOV r12, #0 ; Need to clear r12 for inexact check
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CMP r2, #32 ; See if shift amount >= 32
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BLT shift_right_31_neg ; If not, shift right 31 or less
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MOV r12, r0 ; If >= 32, save lost bits in temp reg,
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MOV r0, r1 ; shift by moving words, and
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MOV r1, #0 ; adjust the shift amount
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SUB r2, r2, #32 ; ..
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shift_right_31_neg
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RSB r3, r2, #32 ; Check for inexact
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ORRS r12, r12, r0, LSL r3 ; ..
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MOV r0, r0, LSR r2 ; Shift the result
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ORR r0, r0, r1, LSL r3 ; ..
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MOV r1, r1, LSR r2 ; ..
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MOVNE r3, #INX_bit ; Set inexact if inexact
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MOVEQ r3, #0 ; Otherwise set to no exceptions
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RSBS r0, r0, #0 ; Negate result
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RSC r1, r1, #0 ; ..
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B __dtoi64_return ; Return
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shift_left_neg
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RSB r2, r2, #0 ; Get left shift amount
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CMP r2, #32 ; If >= 32, shift by moving words, and
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MOVGE r1, r0 ; adjusting shift amount
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MOVGE r0, #0 ; ..
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SUBGE r2, r2, #32 ; ..
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MOV r1, r1, LSL r2 ; Perform rest of shift
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RSB r3, r2, #32 ; ..
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ORR r1, r1, r0, LSR r3 ; ..
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MOV r0, r0, LSL r2 ; ..
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RSBS r0, r0, #0 ; Negate result
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RSC r1, r1, #0 ; ..
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MOV r3, #IVO_bit ; Overflow so set invalid operation
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B __dtoi64_return ; Return
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special_int64_min
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TEQ r1, #0x80000000 ; If shift amount zero and result is
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TEQEQ r0, #0 ; 0x8000000000000000, just leave it
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MOVEQ r3, #0 ; ..
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MOVNE r3, #IVO_bit ; Otherwise it's invalid (overflow)
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RSBS r0, r0, #0 ; Negate result
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RSC r1, r1, #0 ; ..
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__dtoi64_return
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TST r3, #FPECause_mask ; Any exceptions?
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ADDEQ sp, sp, #LOC_SIZE ; If not, pop off saved arg and
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; return
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; return
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ENDIF
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ORR r12, r3, #_FpDToI64 ; Save exception info
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LDR r3, [sp, #OrgOp1h] ; Load original arg
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LDR r2, [sp, #OrgOp1l] ; ..
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STR r0, [sp, #ExDResl] ; Store default result
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STR r1, [sp, #ExDResh] ; ..
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MOV r1, r12 ; Exception information
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ADD r0, sp, #NewResl ; Pointer to new result
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CALL FPE_Raise ; Handle exception information
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ; Load new result
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LDR r1, [sp, #NewResh] ; ..
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ADD sp, sp, #LOC_SIZE ; Pop off exception record and result
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr} ; Return
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BX lr
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ELSE
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LDMFD sp!, {pc} ; Return
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ENDIF
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ENTRY_END __dtoi64
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END
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