107 lines
3.6 KiB
NASM
107 lines
3.6 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity ARM Bootstrap
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;;;
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;;; Xscale varient of the cycle counter routines
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;;;
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|defining ?g_GetCycleCount@Class_Microsoft_Singularity_Isal_Isa@@SA_KXZ| EQU 1
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|defining ?g_EnableCycleCounter@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ| EQU 1
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include hal.inc
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IMPORT |?g_EnableInterrupts@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ|
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IMPORT |?g_DisableInterrupts@Class_Microsoft_Singularity_Isal_Isa@@SA_NXZ|
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TEXTAREA
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CycleCountHi DCD 0 ; storage for upper 32--bits of cycle counter (extended)
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;;;
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;;; Reset cycle counter
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;;;
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;;; "void __cdecl ResetCycleCounter(void)"
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;;;
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LEAF_ENTRY ?ResetCycleCounter@@YAXXZ
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mov r1, #0
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mrc p14, 0, r1, c0, c0, 0 ; read PMCR
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orr r1, r1, #4 ; set C
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mcr p14, 0, r1, c0, c0, 0 ; set PMCR
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bx lr
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LEAF_END
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;;;
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;;; Check for cycle counter wrap and clean
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;;;
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;;; "bool __cdecl CycleCounterWrapped(void)"
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;;;
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LEAF_ENTRY ?CycleCounterWrapped@@YA_NXZ
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mov r1, #0
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bx lr
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LEAF_END
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;;;
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;;; Enable cycle counter
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;;;
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;;; "void __cdecl EnableCycleCounter(void)"
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;;;
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LEAF_ENTRY ?g_EnableCycleCounter@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ
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mov r1, #0
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mrc p14, 0, r1, c0, c1, 0 ; read PMCR
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orr r1, r1, #1 ; set E (enable) bit, disable interrupts
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mcr p14, 0, r1, c0, c1, 0 ; write PMCR
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bx lr
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LEAF_END
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;;;
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;;; Disable cycle counter
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;;;
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;;; "void __cdecl DisableCycleCounter(void)"
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;;;
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LEAF_ENTRY ?DisableCycleCounter@@YAXXZ
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mov r1, #0
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mrc p14, 0, r1, c0, c1, 0 ; read PMCR
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bic r1, r1, #1 ; clear E (enable) bit
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mcr p14, 0, r1, c0, c1, 0 ; write PMCR
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bx lr
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LEAF_END
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;;;
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;;; "public: static unsigned __int64 __cdecl Class_Microsoft_Singularity_Processor::g_GetCycleCount(void)"
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;;;
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NESTED_ENTRY ?g_GetCycleCount@Class_Microsoft_Singularity_Isal_Isa@@SA_KXZ
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stmfd sp!, {r4,lr}
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PROLOG_END
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;; Disable interrupts, r0 becomes do_restore
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bl |?g_DisableInterrupts@Class_Microsoft_Singularity_Isal_Isa@@SA_NXZ|
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mov r2, r0 ; r2 becomes do_restore
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;; Increment high bits if wrap has occurred
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adr r3, CycleCountHi ; r3 is pointer to hi
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ldr r0, [r3] ; r0 is cycle count hi
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mrc p14, 0, r1, c5, c1, 0 ; r1 is FLAG
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ands r1, r1, #1 ; r1 is CCNT wrapped
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mcrne p14, 0, r1, c5, c1, 0 ; clear bit if set
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addne r0, r0, r1 ; increment count hi
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strne r0, [r3] ; store count hi
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mov r3, r0 ; r3 is cycle count hi
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mrc p14, 0, r4, c1, c1, 0 ; r4 becomes cycle cnt
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;; Restore interrupts
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cmp r2, #0
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blne |?g_EnableInterrupts@Class_Microsoft_Singularity_Isal_Isa@@SAXXZ|
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mov r0, r4 ; r0 is cycle count lo
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mov r1, r3 ; r1 is cycle count hi
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ldmfd sp!, {r4,lr}
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bx lr
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NESTED_END
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END
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