298 lines
11 KiB
C#
298 lines
11 KiB
C#
namespace Microsoft.Singularity.Drivers
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{
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public sealed class Atux
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{
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//
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// Offsets from page 146.
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//
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struct Offset
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{
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// ATU Vendor ID Register - ATUVID [p.150]
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const int ATUVID = 0x000;
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// ATU Device ID Register - ATUDID [p.150]
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const int ATUDID = 0x002;
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// ATU Command Register - ATUCMD [p.151]
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const int ATUCMD = 0x004;
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// ATU Status Register - ATUSR [p.152]
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const int ATUSR = 0x006;
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// ATU Revision ID Register - ATURID [p.154]
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const int ATURID = 0x008;
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// ATU Class Code Register - ATUCCR [p.154]
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const int ATUCCR = 0x009;
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// ATU Cacheline Size Register - ATUCLSR [p.155]
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const int ATUCLSR = 0x00C;
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// ATU Latency Timer Register - ATULT [p.155]
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const int ATULT = 0x00D;
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// ATU Header Type Register - ATUHTR [p.156]
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const int ATUHTR = 0x00E;
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// ATU BIST Register - ATUBISTR [p.157]
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const int ATUBISTR = 0x00F;
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// Inbound ATU Base Address Register 0 - IABAR0 [p.158]
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const int IABAR0 = 0x010;
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// Inbound ATU Upper Base Address Register 0 - IAUBAR0 [p.159]
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const int IAUBAR0 = 0x014;
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// Inbound ATU Base Address Register 1 - IABAR1 [p.160]
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const int IABAR1 = 0x018;
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// Inbound ATU Upper Base Address Register 1 - IAUBAR1 [p.161]
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const int IAUBAR1 = 0x01C;
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// Inbound ATU Base Address Register 2 - IABAR2 [p.162]
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const int IABAR2 = 0x020;
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// Inbound ATU Upper Base Address Register 2 - IAUBAR2 [p.163]
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const int IAUBAR2 = 0x024;
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// ATU Subsystem Vendor ID Register - ASVIR [p.164]
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const int ASVIR = 0x02C;
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// ATU Subsystem ID Register - ASIR [p.164]
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const int ASIR = 0x02E;
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// Expansion ROM Base Address Register - ERBAR [p.165]
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const int ERBAR = 0x030;
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// ATU Capabilities Pointer Register - ATU_Cap_Ptr [p.166]
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const int ATU_Cap_Ptr = 0x034;
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// ATU Interrupt Line Register - ATUILR [p.169]
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const int ATUILR = 0x03C;
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// ATU Interrupt Pin Register - ATUIPR [p.170]
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const int ATUIPR = 0x03D;
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// ATU Minimum Grant Register - ATUMGNT [p.170]
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const int ATUMGNT = 0x03E;
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// ATU Maximum Latency Register - ATUMLAT [p.171]
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const int ATUMLAT = 0x03F;
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// Inbound ATU Limit Register 0 - IALR0 [p.172]
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const int IALR0 = 0x040;
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// Inbound ATU Translate Value Register 0 - IATVR0 [p.173]
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const int IATVR0 = 0x044;
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// Inbound ATU Upper Translate Value Register 0 - IAUTVR0 [p.173]
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const int IAUTVR0 = 0x048;
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// Inbound ATU Limit Register 1 - IALR1 [p.174]
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const int IALR1 = 0x04C;
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// Inbound ATU Translate Value Register 1 - IATVR1 [p.175]
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const int IATVR1 = 0x050;
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// Inbound ATU Upper Translate Value Register 1 - IAUTVR1 [p.175]
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const int IAUTVR1 = 0x054;
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// Inbound ATU Limit Register 2 - IALR2 [p.176]
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const int IALR2 = 0x058;
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// Inbound ATU Translate Value Register 2 - IATVR2 [p.177]
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const int IATVR2 = 0x05C;
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// Inbound ATU Upper Translate Value Register 2 - IAUTVR2 [p.177]
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const int IAUTVR2 = 0x060;
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// Expansion ROM Limit Register - ERLR [p.178]
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const int ERLR = 0x064;
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// Expansion ROM Translate Value Register - ERTVR [p.179]
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const int ERTVR = 0x068;
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// Expansion ROM Upper Translate Value Register - ERUTVR [p.179]
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const int ERUTVR = 0x06C;
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// ATU Configuration Register - ATUCR [p.180]
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const int ATUCR = 0x070;
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// PCI Configuration and Status Register - PCSR [p.181]
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const int PCSR = 0x074;
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// ATU Interrupt Status Register - ATUISR [p.184]
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const int ATUISR = 0x078;
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// ATU Interrupt Mask Register - ATUIMR [p.186]
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const int ATUIMR = 0x07C;
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// VPD Capability Identifier Register - VPD_Cap_ID [p.188]
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const int VPD_Cap_ID = 0x090;
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// VPD Next Item Pointer Register - VPD_Next_Item_Ptr [p.188]
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const int VPD_Next_Item_Ptr = 0x091;
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// VPD Address Register - VPDAR [p.189]
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const int VPDAR = 0x092;
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// VPD Data Register - VPDDR [p.189]
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const int VPDDR = 0x094;
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// PM Capability Identifier Register - PM_Cap_ID [p.190]
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const int PM_Cap_ID = 0x098;
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// PM Next Item Pointer Register - PM_Next_Item_Ptr [p.190]
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const int PM_Next_Item_Ptr = 0x099;
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// ATU Power Management Capabilities Register - APMCR [p.191]
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const int APMCR = 0x09A;
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// ATU Power Management Control/Status Register - APMCSR [p.192]
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const int APMCSR = 0x09C;
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// MSI Capability Identifier Register - Cap_ID [p.452]a
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const int Cap_ID = 0x0A0;
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// MSI Next Item Pointer Register - MSI_Next_Ptr [p.453]
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const int MSI_Next_Ptr = 0x0A1;
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// Message Control Register - Message_Control [p.454]
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const int Message_Control = 0x0A2;
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// Message Address Register - Message_Address [p.455]
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const int Message_Address = 0x0A4;
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// Message Upper Address Register - Message_Upper_Address [p.456]
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const int Message_Upper_Address = 0x0A8;
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// Message Data Register - Message_Data [p.457]
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const int Message_Data = 0x0AC;
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// MSI-X Capability Identifier Register - MSI_X_Cap_ID [p.458]
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const int MSI_X_Cap_ID = 0x0B0;
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// MSI-X Next Item Pointer Register - MSI_X_Next_Item_Ptr [p.459]
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const int MSI_X_Next_Item_Ptr = 0x0B1;
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// MSI-X Message Control Register - MSI_X_MCR [p.460]
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const int MSI_X_MCR = 0x0B2;
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// MSI-X Table Offset Register - MSI_X_Table_Offset [p.461]
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const int MSI_X_Table_Offset = 0x0B4;
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// MSI-X Pending Bit Array Offset Register - MSI_X_PBA_Offset [p.462]
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const int MSI_X_PBA_Offset = 0x0B8;
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// ATU Scratch Pad Register - ATUSPR [p.193]
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const int ATUSPR = 0x0CC;
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// PCI-X Capability Identifier Register - PCI_X_Cap_ID [p.193]
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const int PCI_X_Cap_ID = 0x0D0;
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// PCI-X Next Item Pointer Register - PCI_X_Next_Item_Ptr [p.194]
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const int PCI_X_Next_Item_Ptr = 0x0D1;
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// PCI-X Command Register - PCIXCMD [p.194]
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const int PCIXCMD = 0x0D2;
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// PCI-X Status Register - PCIXSR [p.196]
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const int PCIXSR = 0x0D4;
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// ECC Control and Status Register - ECCCSR [p.198]
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const int ECCCSR = 0x0D8;
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// ECC First Address Register - ECCFAR [p.201]
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const int ECCFAR = 0x0DC;
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// ECC Second Address Register - ECCSAR [p.202]
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const int ECCSAR = 0x0E0;
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// ECC Attribute Register - ECCAR [p.203]
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const int ECCAR = 0x0E4;
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// CompactPCI Hot-Swap Capability ID Register - HS_CAPID [p.203]
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const int HS_CAPID = 0x0E8;
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// Offset EDh: Next Item Pointer - HS_NXTP [p.204]
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const int HS_NXTP = 0x0E9;
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// Hot-Swap Control/Status Register - HS_CNTRL [p.205]
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const int HS_CNTRL = 0x0EA;
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// Inbound ATU Base Address Register 3 - IABAR3 [p.207]
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const int IABAR3 = 0x200;
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// Inbound ATU Upper Base Address Register 3 - IAUBAR3 [p.208]
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const int IAUBAR3 = 0x204;
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// Inbound ATU Limit Register 3 - IALR3 [p.209]
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const int IALR3 = 0x208;
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// Inbound ATU Translate Value Register 3 - IATVR3 [p.210]
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const int IATVR3 = 0x20C;
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// Inbound ATU Upper Translate Value Register 3 - IAUTVR3 [p.210]
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const int IAUTVR3 = 0x210;
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// Outbound I/O Base Address Register - OIOBAR [p.211]
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const int OIOBAR = 0x300;
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// Outbound I/O Window Translate Value Register - OIOWTVR [p.212]
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const int OIOWTVR = 0x304;
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// Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 [p.213]
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const int OUMBAR0 = 0x308;
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// Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 [p.214]
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const int OUMWTVR0 = 0x30C;
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// Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 [p.215]
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const int OUMBAR1 = 0x310;
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// Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 [p.216]
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const int OUMWTVR1 = 0x314;
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// Outbound Upper Memory Window Base Address Register 2 - OUMBAR2 [p.217]
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const int OUMBAR2 = 0x318;
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// Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2 [p.218]
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const int OUMWTVR2 = 0x31C;
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// Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 [p.219]
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const int OUMBAR3 = 0x320;
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// Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3 [p.220]
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const int OUMWTVR3 = 0x324;
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// Outbound Configuration Cycle Address Register - OCCAR [p.221]
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const int OCCAR = 0x330;
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// Outbound Configuration Cycle Data Register - OCCDR [p.222]
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const int OCCDR = 0x334;
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// Outbound Configuration Cycle Function Number - OCCFN [p.222]
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const int OCCFN = 0x338;
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// PCI Interface Error Control and Status Register - PIECSR [p.223]
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const int PIECSR = 0x380;
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// PCI Interface Error Address Register - PCIEAR [p.224]
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const int PCIEAR = 0x384;
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// PCI Interface Error Upper Address Register - PCIEUAR [p.225]
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const int PCIEUAR = 0x388;
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// PCI Interface Error Context Address Register - PCIECAR [p.226]
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const int PCIECAR = 0x38C;
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// Internal Arbiter Control Register - IACR [p.227]
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const int IACR = 0x394;
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// Multi-Transaction Timer - MTT [p.228]
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const int MTT = 0x398;
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}
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}
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}
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