172 lines
4.9 KiB
C#
172 lines
4.9 KiB
C#
//////////////////////////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// This file defines an architecture-neutral encapsulation of the low-level information
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// saved during an interrupt dispatch.
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//
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using System;
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using System.Runtime.InteropServices;
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using System.Runtime.CompilerServices;
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#if ISA_IX
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using Microsoft.Singularity.Isal.IX;
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#elif ISA_ARM
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using Microsoft.Singularity.Isal.Arm;
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#endif
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namespace Microsoft.Singularity.Isal
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{
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// InterruptContext is the lightweight context which is pushed on the stack
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// during interrupt generation. This is the minimal context save we will
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// perform for any interrupt processing. (Note that it includes caller
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// saved registers so we can use C code.)
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[NoCCtor]
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[AccessedByRuntime("referenced in c++", AllFields = true)]
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[CLSCompliant(false)]
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[StructLayout(LayoutKind.Sequential)]
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public struct InterruptContext
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{
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#if ISA_IX
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// Vector constants
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public const int VectorExceptionMax = 0x20;
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public const int VectorSchedulerMin = 0x21;
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#if ISA_IX64
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// Caller-saved registers (which get saved by our handler routine)
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public UIntPtr r11;
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public UIntPtr r10;
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public UIntPtr r9;
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public UIntPtr r8;
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#endif //ISA_IX64
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// Caller-saved registers (which get saved by our handler routine)
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public UIntPtr dx;
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public UIntPtr cx;
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public UIntPtr ax;
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// Interrupt information pushed as part of interrupt dispatch
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public UIntPtr vector;
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public UIntPtr err;
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// Interruption context
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public UIntPtr ip;
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public UIntPtr cs;
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public UIntPtr fl;
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// This stack info is valid only in cases of cross-ring interrupts; otherwise
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// we stay on the same stack and pop to this level (ignoring these two fields.)
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public UIntPtr sp;
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public UIntPtr ss;
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#elif ISA_ARM
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// Unbanked caller-saved registers.
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public uint r0;
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public uint r1;
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public uint r2;
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public uint r3;
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public uint r12;
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public uint pc; // aka r15
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// Banked caller-saved registers.
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public uint sp; // aka r13
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public uint lr; // aka r14
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// Resume proessor status register.
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public uint cpsr;
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// Interrupt information.
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public uint vector;
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public uint instruction;
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#endif
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[NoHeapAllocation]
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public bool IsException()
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{
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#if ISA_IX
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return (vector < 0x20);
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#elif ISA_ARM
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return (vector < ExceptionVector.Irq);
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#endif
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}
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public byte ExceptionId
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{
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[NoHeapAllocation]
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get {
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return (byte)vector;
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}
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}
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public UIntPtr InstructionPointer
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{
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[NoHeapAllocation]
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get {
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#if ISA_IX
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return (UIntPtr)ip;
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#elif ISA_ARM
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return (UIntPtr)pc;
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#endif
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}
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}
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public UIntPtr StackPointer
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{
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[NoHeapAllocation]
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get {
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#if ISA_IX86
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if ((cs & 0x3) == (Isa.GetCs() & 0x3)) {
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unsafe {
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fixed (UIntPtr *p = &sp) {
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return *p;
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}
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}
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}
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else {
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return sp;
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}
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#elif ISA_IX64
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return sp;
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#elif ISA_ARM
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return sp;
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#endif
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}
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}
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[NoHeapAllocation]
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public unsafe void Display()
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{
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#if ISA_IX86
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DebugStub.WriteLine(" eax={0:x8} ecx={1:x8} edx={2:x8}",
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__arglist(ax, cx, dx));
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DebugStub.WriteLine(" esp[x-ring only]={0:x8}",
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__arglist(sp));
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DebugStub.WriteLine(" eip={0:x8} efl={1:x8}",
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__arglist(ip, fl));
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#elif ISA_IX64
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DebugStub.WriteLine(" rax={0:x16} rcx={1:x16} rdx={2:x16}",
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__arglist(ax, cx, dx));
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DebugStub.WriteLine(" rsp={0:x16}",
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__arglist(sp));
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DebugStub.WriteLine(" rip={0:x16} rfl={1:x16}",
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__arglist(ip, fl));
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#elif ISA_ARM
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DebugStub.WriteLine("pc={0:x8} sp={1:x8} lr={2:x8} sr={3:x8}",
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__arglist(pc, sp, lr, cpsr));
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DebugStub.WriteLine("r0={0:x8} r1={1:x8} r2={2:x8} r3={3:x8}",
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__arglist(r0, r1, r2, r3));
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#endif
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}
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}
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}
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