793 lines
25 KiB
NASM
793 lines
25 KiB
NASM
;**********************************************************************
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; void *
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; memmove( void *dest, const void *src, size_t count );
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;
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; memmove() copies 'count' bytes from the source buffer to the
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; destination buffer and returns a pointer to the destination
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; buffer. memmove() guarantees the overlaping buffers will
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; be copied successfully.
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;
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;**********************************************************************
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;
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; $$$ NOTE $$$: These routines use the LDRH opcode which is not
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; supported on ARM 3 or 3T architectures. Hence, these routines
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; assume ARM 4 or later architectures.
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;
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;**********************************************************************
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OPT 2 ; disable listing
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INCLUDE kxarm.inc
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OPT 1 ; reenable listing
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dest RN R0
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source RN R1
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count RN R2
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temp1 RN R3
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temp2 RN R4
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temp3 RN R5
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temp4 RN R12
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IF Thumbing
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THUMBAREA
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ENDIF
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NESTED_ENTRY memmove
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ROUT
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IF Thumbing
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; Switch from Thumb mode to ARM mode
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DCW 0x4778 ; bx pc
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DCW 0x46C0 ; nop
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ENDIF
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STMDB sp!, {dest,temp2,temp3,lr} ; save registers
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PROLOG_END
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;if source comes before destination copy from tail to head
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CMP source, dest
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BGE HEAD_TO_TAIL ; if source < dest
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;**********************************************************************
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; Copy from tail to head to avoid source overwrite because the source
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; precedes the destination
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;**********************************************************************
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TAILTOHEAD
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;Move pointers to the tails
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ADD source, source, count
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ADD dest, dest, count
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CMP count, #8 ;if < 8 bytes, byte moves
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BLT TTH_BYTEMOVE4
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;check if destination is word aligned, if not then align it
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ANDS temp1, dest, #3 ; 2-3 cycles
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BEQ TTH_CHKSRC_ALIGN
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;
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;read 1 to 3 bytes until the destination is word aligned, then
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;see if the source is word aligned, if it is then go back to
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;word length moves, else continue on with single byte moves
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;
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TTH_ATTEMPTALIGN
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LDRB temp2, [source, #-1]! ; 8 cycles/1-3 bytes
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CMP temp1, #2
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STRB temp2, [dest, #-1]!
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LDRGEB temp3, [source, #-1]!
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SUB count, count, temp1
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LDRGTB temp2, [source, #-1]!
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STRGEB temp3, [dest, #-1]!
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STRGTB temp2, [dest, #-1]!
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; Check if source is word aligned, if not check for word
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; alignment.
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TTH_CHKSRC_ALIGN
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TST source, #1 ; 3-7 cycles
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BNE TTH_UNALIGNED ; Unaligned moves
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TST source, #2
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BNE TTH_HWORD_ALIGNED ; Half Word aligned
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;
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; Word aligned source and destination.
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; Move blocks of 32 bytes until we have less than 32 bytes left,
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; then divide moves in half down to less than 4 then jump to byte
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; moves.
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; NOTE: Because of the overhead of pushing registers for 32 byte
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; moves it is actually more efficient to use 16 byte moves for
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; blocks of less than 128 bytes.
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;
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TTH_REALIGNED
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SUBS count, count, #32 ; 2-3 cycles
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BLT TTH_BLK16
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TTH_BLK32 ; 20 cycles/32 bytes
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LDMDB source!, {temp1,temp2,temp3,lr}
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STMDB dest!, {temp1,temp2,temp3,lr}
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LDMDB source!, {temp1,temp2,temp3,lr}
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SUBS count, count, #32
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STMDB dest!, {temp1,temp2,temp3,lr}
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BGE TTH_BLK32
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TTH_BLK16 ; 10 cycles/16 bytes
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ADDS count, count, #16
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LDMGEDB source!, {temp1, temp2, temp3, lr}
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SUBGE count, count, #16
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STMGEDB dest!, {temp1, temp2, temp3, lr}
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TTH_BLK8 ; 6 cycles / 8 bytes
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ADDS count, count, #8
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LDMGEDB source!, {temp1, temp2}
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SUBGE count, count, #8
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STMGEDB dest!, {temp1, temp2}
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TTH_BLK4 ; 6-9 cycles/4 bytes
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ADDS count, count, #4
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LDRGE temp1, [source, #-4]!
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STRGE temp1, [dest, #-4]!
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TTH_WORD_BYTES
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ADDLTS count, count, #4
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BEQ TTH_WORD_EXIT
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LDRB temp1, [source, #-1]! ; 4-7 cycles/1 byte
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CMP count, #2
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STRB temp1, [dest, #-1]!
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LDRGEB temp2, [source, #-1]!
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LDRGTB temp3, [source, #-1]! ; 8 cycles/1-2 bytes
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STRGEB temp2, [dest, #-1]!
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STRGTB temp3, [dest, #-1]!
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TTH_WORD_EXIT
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {dest, temp2, temp3, lr}
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BX lr
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ELSE
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LDMIA sp!, {dest, temp2, temp3, pc}
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ENDIF
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;
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; Source and Destination are half word aligned.
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; For blocks < 96 bytes it's actually more efficient to jump to
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; the 8 byte copy than take the hit for setup time on 32 byte copy.
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;
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TTH_HWORD_ALIGNED
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LDRH lr, [source, #-2]! ; 4-5 cycles
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SUBS count, count, #32
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MOV lr, lr, LSL #16
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BLT TTH_HWORD8_TST
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TTH_HWORD32 ; 35 cycles/32 bytes
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LDMDB source!, {temp1,temp2,temp3,temp4}
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SUBS count, count, #32
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ORR lr, lr, temp4, LSR #16
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MOV temp4, temp4, LSL #16
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ORR temp4, temp4, temp3, LSR #16
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MOV temp3, temp3, LSL #16
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ORR temp3, temp3, temp2, LSR #16
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MOV temp2, temp2, LSL #16
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ORR temp2, temp2, temp1, LSR #16
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 21-32
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STR temp2, [dest, #-4]! ; Store bytes 17-20
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MOV lr, temp1, LSL #16
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LDR temp4, [source, #-4]!
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LDMDB source!, {temp1,temp2,temp3}
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ORR lr, lr, temp4, LSR #16
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MOV temp4, temp4, LSL #16
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ORR temp4, temp4, temp3, LSR #16
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MOV temp3, temp3, LSL #16
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ORR temp3, temp3, temp2, LSR #16
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MOV temp2, temp2, LSL #16
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ORR temp2, temp2, temp1, LSR #16
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 5-16
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STR temp2, [dest, #-4]! ; Store bytes 1-4
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MOV lr, temp1, LSL #16
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BGE TTH_HWORD32
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TTH_HWORD8_TST
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ADDS count, count, #24
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BLT TTH_HWORD4
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TTH_HWORD8 ; 11 cycles/8 bytes
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LDMDB source!, {temp2, temp3}
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SUBS count, count, #8
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ORR lr, lr, temp3, LSR #16
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MOV temp3, temp3, LSL #16
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ORR temp3, temp3, temp2, LSR #16
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STR lr, [dest, #-4]!
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STR temp3, [dest, #-4]!
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MOV lr, temp2, LSL #16
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BGE TTH_HWORD8
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TTH_HWORD4 ; 3-12 cycles/4 bytes
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ADDS count, count, #4
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BLT TTH_HWORD_BYTES
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LDR temp1, [source, #-4]!
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ORR lr, lr, temp1, LSR #16
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STR lr, [dest, #-4]!
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MOV lr, temp1, LSL #16
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TTH_HWORD_BYTES
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ADDLTS count, count, #4
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BEQ TTH_HWORD_EXIT
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MOV lr, lr, LSR #16 ; 11 cycles/1-3 bytes
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CMP count, #2
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MOVLT lr, lr, LSR #8
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STRLTB lr, [dest, #-1]!
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LDRGTB temp1, [source, #-1]!
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STRGEH lr, [dest, #-2]!
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STRGTB temp1, [dest, #-1]!
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TTH_HWORD_EXIT
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {dest, temp2, temp3, lr}
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BX lr
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ELSE
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LDMIA sp!, {dest, temp2, temp3, pc}
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ENDIF
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TTH_UNALIGNED
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TST source, #2
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BEQ TTH_OFFONE
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;
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; 3 Byte difference between word and source.
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;
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TTH_OFFTHREE
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LDRB temp3, [source, #-1]! ; 5-6 cycles
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LDRH lr, [source, #-2]!
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SUBS count, count, #32
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ORR lr, lr, temp3, LSL #16
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MOV lr, lr, LSL #8
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BLT TTH_OFFTHREE8_TST
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TTH_OFFTHREE32 ; 35 cycles/32 bytes
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LDMDB source!, {temp1,temp2,temp3,temp4}
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SUBS count, count, #32
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ORR lr, lr, temp4, LSR #24
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MOV temp4, temp4, LSL #8
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ORR temp4, temp4, temp3, LSR #24
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MOV temp3, temp3, LSL #8
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ORR temp3, temp3, temp2, LSR #24
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MOV temp2, temp2, LSL #8
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ORR temp2, temp2, temp1, LSR #24
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 21-32
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STR temp2, [dest, #-4]! ; Store bytes 17-20
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MOV lr, temp1, LSL #8
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LDR temp4, [source, #-4]!
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LDMDB source!, {temp1,temp2,temp3}
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ORR lr, lr, temp4, LSR #24
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MOV temp4, temp4, LSL #8
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ORR temp4, temp4, temp3, LSR #24
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MOV temp3, temp3, LSL #8
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ORR temp3, temp3, temp2, LSR #24
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MOV temp2, temp2, LSL #8
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ORR temp2, temp2, temp1, LSR #24
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 5-16
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STR temp2, [dest, #-4]! ; Store bytes 1-4
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MOV lr, temp1, LSL #8
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BGE TTH_OFFTHREE32
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TTH_OFFTHREE8_TST
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ADDS count, count, #24
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BLT TTH_OFFTHREE4
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TTH_OFFTHREE8 ; 11 cycles/8 bytes
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LDMDB source!, {temp1, temp2}
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SUBS count, count, #8
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ORR lr, lr, temp2, LSR #24
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MOV temp2, temp2, LSL #8
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ORR temp2, temp2, temp1, LSR #24
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STR lr, [dest, #-4]! ; Store bytes 5-8
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STR temp2, [dest, #-4]! ; Store bytes 1-4
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MOV lr, temp1, LSL #8
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BGE TTH_OFFTHREE8
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TTH_OFFTHREE4 ; 3-11 cycles/4 bytes
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ADDS count, count, #4
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BLT TTH_OFFTHREE_BYTES
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LDR temp3, [source, #-4]!
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ORR lr, lr, temp3, LSR #24
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STR lr, [dest, #-4]!
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MOV lr, temp3, LSL #8
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TTH_OFFTHREE_BYTES
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ADDLTS count, count, #4
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BEQ TTH_OFFTHREE_EXIT
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MOV lr, lr, LSR #8 ; 11 cycles/1-3 bytes
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CMP count, #2
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MOVLT temp1, lr, LSR #16
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STRLTB temp1, [dest, #-1]!
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MOVGE temp1, lr, LSR #8
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STRGEH temp1, [dest, #-2]!
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STRGTB lr, [dest, #-1]!
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TTH_OFFTHREE_EXIT
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {dest, temp2, temp3, lr}
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BX lr
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ELSE
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LDMIA sp!, {dest, temp2, temp3, pc}
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ENDIF
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;
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; One Byte difference between word and source.
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;
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TTH_OFFONE
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LDRB lr, [source, #-1]!
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SUBS count, count, #32 ; 2-3 cycles
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MOV lr, lr, LSL #24
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BLT TTH_OFFONE8_TST
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TTH_OFFONE32 ; 35 cycles/32 bytes
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LDMDB source!, {temp1,temp2,temp3,temp4}
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SUBS count, count, #32 ; avoid result delay
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ORR lr, lr, temp4, LSR #8
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MOV temp4, temp4, LSL #24
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ORR temp4, temp4, temp3, LSR #8
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MOV temp3, temp3, LSL #24
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ORR temp3, temp3, temp2, LSR #8
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MOV temp2, temp2, LSL #24
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ORR temp2, temp2, temp1, LSR #8
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 21-32
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STR temp2, [dest, #-4]! ; STore bytes 17-20
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MOV lr, temp1, LSL #24
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LDR temp4, [source, #-4]!
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LDMDB source!, {temp1,temp2,temp3}
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ORR lr, lr, temp4, LSR #8
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MOV temp4, temp4, LSL #24
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ORR temp4, temp4, temp3, LSR #8
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MOV temp3, temp3, LSL #24
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ORR temp3, temp3, temp2, LSR #8
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MOV temp2, temp2, LSL #24
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ORR temp2, temp2, temp1, LSR #8
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STMDB dest!, {temp3,temp4,lr} ; Store bytes 5-16
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STR temp2, [dest, #-4]! ; STore bytes 1-4
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MOV lr, temp1, LSL #24
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BGE TTH_OFFONE32
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TTH_OFFONE8_TST
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ADDS count, count, #24
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BLT TTH_OFFONE4
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TTH_OFFONE8 ; 11 cycles/8 bytes
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LDMDB source!, {temp2, temp3}
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SUBS count, count, #8
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ORR lr, lr, temp3, LSR #8
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MOV temp3, temp3, LSL #24
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STR lr, [dest, #-4]!
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ORR temp3, temp3, temp2, LSR #8
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STR temp3, [dest, #-4]!
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MOV lr, temp2, LSL #24
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BGE TTH_OFFONE8
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TTH_OFFONE4 ; 8-10 cycles/4 bytes
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ADDS count, count, #4
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BLT TTH_OFFONE_BYTES
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LDR temp3, [source, #-4]!
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ORR lr, lr, temp3, LSR #8
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STR lr, [dest, #-4]!
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MOV lr, temp3, LSL #24
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TTH_OFFONE_BYTES ; 13 cycles/1-3 bytes
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ADDLTS count, count, #4
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BEQ TTH_OFFONE_EXIT
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MOV lr, lr, LSR #24
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CMP count, #2
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STRB lr, [dest, #-1]!
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BLT TTH_OFFONE_EXIT
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LDRGEB temp1, [source, #-1]!
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LDRGTB temp2, [source, #-1]!
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STRGEB temp1, [dest, #-1]!
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STRGTB temp2, [dest, #-1]!
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TTH_OFFONE_EXIT
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {dest, temp2, temp3, lr}
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BX lr
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ELSE
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LDMIA sp!, {dest, temp2, temp3, pc}
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ENDIF
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TTH_BYTEMOVE4 ; 12 cycles/4 bytes
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CMP count, #4
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BLT TTH_LAST3
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LDRB temp1, [source, #-1]!
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LDRB temp2, [source, #-1]!
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LDRB temp3, [source, #-1]!
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LDRB lr, [source, #-1]!
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SUB count, count, #4
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STRB temp1, [dest, #-1]!
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STRB temp2, [dest, #-1]!
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STRB temp3, [dest, #-1]!
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STRB lr, [dest, #-1]!
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; Move the last 0-3 bytes
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TTH_LAST3
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CMP count, #0 ; 2 or 5 cycles
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BEQ TTH_BYTEMOVE_EXIT
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;
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;single byte moves
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;
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TTH_BYTEMOVE ; 11 cycles/1-3 bytes
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LDRB temp1, [source, #-1]!
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CMP count, #2
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STRB temp1, [dest, #-1]!
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BLT TTH_BYTEMOVE_EXIT
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LDRGEB temp2, [source, #-1]!
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LDRGTB temp3, [source, #-1]!
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STRGEB temp2, [dest, #-1]!
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STRGTB temp3, [dest, #-1]!
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TTH_BYTEMOVE_EXIT
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IF Interworking :LOR: Thumbing
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LDMIA sp!, {dest, temp2, temp3, lr}
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BX lr
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ELSE
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LDMIA sp!, {dest, temp2, temp3, pc}
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ENDIF
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;**********************************************************************
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; Copy from head to tail to avoid source overwrite because the source
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; destination the source
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;**********************************************************************
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HEAD_TO_TAIL
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;if LT 8 bytes store them and exit
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CMP count, #8 ; 2-3 cycles
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BLT BYTEMOVE4
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;Check alignment of parameters
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ANDS temp1, dest, #3 ; 2-3 cycles
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BEQ SRCALIGN
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; destination is at least 1 byte misaligned
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; Read and write (4 - alignment) bytes to align destination.
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RSB temp1, temp1, #4 ; 9 cycles
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LDRB temp2, [source], #1
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CMP temp1, #2
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STRB temp2, [dest], #1
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LDRGEB temp3, [source], #1 ; >= 2 == at least 2 bytes
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LDRGTB temp2, [source], #1 ; > 2 == 3 bytes unaligned
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SUB count, count, temp1
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STRGEB temp3, [dest], #1
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STRGTB temp2, [dest], #1
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SRCALIGN ; 3 - 7 cycles
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TST source, #1 ; save alignment of src
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BNE UNALIGNED ; src 3 byte unaligned.
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TST source, #2
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BNE HWORDMOVE ; src and dst are hword aligned
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;
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;word aligned source and destination, move blocks of 32 bytes
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;until we have less than 32 bytes left, then divide moves in
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;half down to less than 4, where we will move the last 3 or less
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;bytes
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;
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WORDMOVE
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SUBS count, count, #32 ; 2-3 cycles
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BLT BLK16
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BLK32 ; 20 cycles/32 bytes
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LDMIA source!, {temp1,temp2,temp3,lr}
|
|
STMIA dest!, {temp1,temp2,temp3,lr}
|
|
LDMIA source!, {temp1,temp2,temp3,lr}
|
|
SUBS count, count, #32
|
|
STMIA dest!, {temp1,temp2,temp3,lr}
|
|
BGE BLK32
|
|
|
|
BLK16 ; 11-4 cycles/16 bytes
|
|
ADDS count, count, #16
|
|
LDMGEIA source!, {temp1, temp2, temp3, lr}
|
|
STMGEIA dest!, {temp1, temp2, temp3, lr}
|
|
BEQ WORD_BYTES_EXIT
|
|
SUBGTS count, count, #16
|
|
|
|
BLK8 ; 6 cycles/8 bytes
|
|
ADDS count, count, #8
|
|
LDMGEIA source!, {temp1, temp2}
|
|
SUBGE count, count, #8
|
|
STMGEIA dest!, {temp1, temp2}
|
|
|
|
BLK4
|
|
ADDS count, count, #4 ; 6-9 cycles/4 bytes
|
|
LDRGE temp1, [source], #4
|
|
STRGE temp1, [dest], #4
|
|
|
|
WORD_BYTES
|
|
ADDLTS count, count, #4
|
|
BEQ WORD_BYTES_EXIT ; On zero, Return to caller
|
|
|
|
LDR temp1, [source], #4 ; 10 cycles/1-3 bytes
|
|
CMP count, #2
|
|
STRGEH temp1, [dest], #2
|
|
STRLTB temp1, [dest], #1
|
|
MOVGT temp1, temp1, LSR #16
|
|
STRGTB temp1, [dest], #1
|
|
|
|
WORD_BYTES_EXIT
|
|
|
|
IF Interworking :LOR: Thumbing
|
|
LDMIA sp!, {dest, temp2, temp3, lr}
|
|
BX lr
|
|
ELSE
|
|
LDMIA sp!, {dest, temp2, temp3, pc}
|
|
ENDIF
|
|
|
|
;
|
|
; half word align source and destination
|
|
;
|
|
HWORDMOVE ; 2-3 cycles
|
|
LDRH temp1, [source], #2
|
|
SUBS count, count, #32
|
|
BLT HWORD8_TST
|
|
|
|
HWORD32 ; 35 cycles/32 bytes
|
|
LDMIA source!, {temp2,temp3,temp4,lr}
|
|
ORR temp1, temp1, temp2, LSL #16
|
|
MOV temp2, temp2, LSR #16
|
|
ORR temp2, temp2, temp3, LSL #16
|
|
MOV temp3, temp3, LSR #16
|
|
ORR temp3, temp3, temp4, LSL #16
|
|
MOV temp4, temp4, LSR #16
|
|
ORR temp4, temp4, lr, LSL #16
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 1-16
|
|
MOV temp1, lr, LSR #16
|
|
LDMIA source!, {temp2,temp3,temp4,lr}
|
|
ORR temp1, temp1, temp2, LSL #16
|
|
MOV temp2, temp2, LSR #16
|
|
ORR temp2, temp2, temp3, LSL #16
|
|
MOV temp3, temp3, LSR #16
|
|
ORR temp3, temp3, temp4, LSL #16
|
|
MOV temp4, temp4, LSR #16
|
|
ORR temp4, temp4, lr, LSL #16
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 17-32
|
|
SUBS count, count, #32
|
|
MOV temp1, lr, LSR #16
|
|
BGE HWORD32
|
|
|
|
HWORD8_TST
|
|
ADDS count, count, #24
|
|
BLT HWORD4
|
|
|
|
HWORD8 ; 11 cycles/8 bytes
|
|
LDMIA source!, {temp2,temp3}
|
|
ORR temp1, temp1, temp2, LSL #16
|
|
MOV temp2, temp2, LSR #16
|
|
ORR temp2, temp2, temp3, LSL #16
|
|
STMIA dest!, {temp1, temp2}
|
|
SUBS count, count, #8
|
|
MOV temp1, temp3, LSR #16
|
|
BGE HWORD8
|
|
|
|
HWORD4 ; 3-7 cycles/4 bytes
|
|
ADDS count, count, #4
|
|
BLT HWORD_BYTES
|
|
LDR temp2, [source], #4
|
|
ORR temp1, temp1, temp2, LSL #16
|
|
STR temp1, [dest], #4
|
|
MOV temp1, temp2, LSR #16
|
|
|
|
HWORD_BYTES ; 5-11 cycles/1-3 bytes
|
|
ADDLTS count, count, #4
|
|
BEQ HWORD_BYTES_EXIT ; On zero, Return to caller
|
|
CMP count, #2
|
|
STRLTB temp1, [dest], #1
|
|
LDRGTB temp2, [source], #1
|
|
STRGEH temp1, [dest], #2
|
|
STRGTB temp2, [dest], #1
|
|
|
|
HWORD_BYTES_EXIT
|
|
|
|
IF Interworking :LOR: Thumbing
|
|
LDMIA sp!, {dest, temp2, temp3, lr}
|
|
BX lr
|
|
ELSE
|
|
LDMIA sp!, {dest, temp2, temp3, pc}
|
|
ENDIF
|
|
|
|
;
|
|
; Unaligned Moves
|
|
;
|
|
UNALIGNED
|
|
TST source, #2
|
|
BEQ UNALIGNED1
|
|
|
|
UNALIGNED3 ; 3-4 cycles
|
|
LDRB temp1, [source], #1
|
|
SUBS count, count, #32
|
|
BLT OFFTHREE8_TST
|
|
|
|
OFFTHREE32 ; 35 cycles/32 bytes
|
|
LDMIA source!, {temp2,temp3,temp4,lr}
|
|
ORR temp1, temp1, temp2, LSL #8
|
|
MOV temp2, temp2, LSR #24
|
|
ORR temp2, temp2, temp3, LSL #8
|
|
MOV temp3, temp3, LSR #24
|
|
ORR temp3, temp3, temp4, LSL #8
|
|
MOV temp4, temp4, LSR #24
|
|
ORR temp4, temp4, lr, LSL #8
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 1-16
|
|
MOV temp1, lr, LSR #24
|
|
LDMIA source!, {temp2,temp3,temp4,lr}
|
|
ORR temp1, temp1, temp2, LSL #8
|
|
MOV temp2, temp2, LSR #24
|
|
ORR temp2, temp2, temp3, LSL #8
|
|
MOV temp3, temp3, LSR #24
|
|
ORR temp3, temp3, temp4, LSL #8
|
|
MOV temp4, temp4, LSR #24
|
|
ORR temp4, temp4, lr, LSL #8
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 17-32
|
|
SUBS count, count, #32
|
|
MOV temp1, lr, LSR #24
|
|
BGE OFFTHREE32
|
|
|
|
OFFTHREE8_TST
|
|
ADDS count, count, #24
|
|
BLT OFFTHREE4
|
|
|
|
OFFTHREE8 ; 11 cycles/8 bytes
|
|
LDMIA source!, {temp2,temp3}
|
|
ORR temp1, temp1, temp2, LSL #8
|
|
MOV temp2, temp2, LSR #24
|
|
ORR temp2, temp2, temp3, LSL #8
|
|
STMIA dest!, {temp1, temp2}
|
|
SUBS count, count, #8
|
|
MOV temp1, temp3, LSR #24
|
|
BGE OFFTHREE8
|
|
|
|
OFFTHREE4 ; 3-7 cycles/4 bytes
|
|
ADDS count, count, #4
|
|
BLT OFFTHREE_BYTES
|
|
LDR temp2, [source], #4
|
|
ORR temp1, temp1, temp2, LSL #8
|
|
STR temp1, [dest], #4
|
|
MOV temp1, temp2, LSR #24
|
|
|
|
OFFTHREE_BYTES ; 5-12 cycles/ 1-3 bytes
|
|
ADDLTS count, count, #4
|
|
BEQ OFFTHREE_EXIT ; On zero, Return to caller
|
|
CMP count, #2
|
|
LDRGEH temp2, [source], #2
|
|
STRB temp1, [dest], #1
|
|
STRGEB temp2, [dest], #1
|
|
MOVGT temp2, temp2, LSR #8
|
|
STRGTB temp2, [dest], #1
|
|
|
|
OFFTHREE_EXIT
|
|
|
|
IF Interworking :LOR: Thumbing
|
|
LDMIA sp!, {dest, temp2, temp3, lr}
|
|
BX lr
|
|
ELSE
|
|
LDMIA sp!, {dest, temp2, temp3, pc} ; On zero, Return to caller
|
|
ENDIF
|
|
|
|
;
|
|
; Source is one byte from word alignment.
|
|
; Read a byte & half word then multiple words and a byte. Then
|
|
; shift and ORR them into consecutive words for STM writes
|
|
UNALIGNED1 ; 5-6 cycles
|
|
LDRB temp1, [source], #1
|
|
LDRH temp2, [source], #2
|
|
SUBS count, count, #32
|
|
ORR temp1, temp1, temp2, LSL #8
|
|
BLT OFFONE8_TST
|
|
|
|
OFFONE32 ; 35 cycles/32 bytes
|
|
LDMIA source!, {temp2, temp3, temp4, lr}
|
|
ORR temp1, temp1, temp2, LSL #24
|
|
MOV temp2, temp2, LSR #8
|
|
ORR temp2, temp2, temp3, LSL #24
|
|
MOV temp3, temp3, LSR #8
|
|
ORR temp3, temp3, temp4, LSL #24
|
|
MOV temp4, temp4, LSR #8
|
|
ORR temp4, temp4, lr, LSL #24
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 1-16
|
|
MOV temp1, lr, LSR #8
|
|
LDMIA source!, {temp2,temp3,temp4,lr}
|
|
ORR temp1, temp1, temp2, LSL #24
|
|
MOV temp2, temp2, LSR #8
|
|
ORR temp2, temp2, temp3, LSL #24
|
|
MOV temp3, temp3, LSR #8
|
|
ORR temp3, temp3, temp4, LSL #24
|
|
MOV temp4, temp4, LSR #8
|
|
ORR temp4, temp4, lr, LSL #24
|
|
STMIA dest!, {temp1,temp2,temp3,temp4} ; Store bytes 17-32
|
|
SUBS count, count, #32
|
|
MOV temp1, lr, LSR #8
|
|
BGE OFFONE32
|
|
|
|
OFFONE8_TST
|
|
ADDS count, count, #24
|
|
BLT OFFONE4
|
|
|
|
OFFONE8 ; 11 cycles/8 bytes
|
|
LDMIA source!, {temp2,temp3}
|
|
ORR temp1, temp1, temp2, LSL #24
|
|
MOV temp2, temp2, LSR #8
|
|
ORR temp2, temp2, temp3, LSL #24
|
|
STMIA dest!, {temp1,temp2}
|
|
SUBS count, count, #8
|
|
MOV temp1, temp3, LSR #8
|
|
BGE OFFONE8
|
|
|
|
OFFONE4 ; 3-9 cycles/4 bytes
|
|
ADDS count, count, #4
|
|
BLT OFFONE_BYTES
|
|
LDR temp2, [source], #4
|
|
ORR temp1, temp1, temp2, LSL #24
|
|
STR temp1, [dest], #4
|
|
BEQ OFFONE_EXIT
|
|
MOV temp1, temp2, LSR #8
|
|
|
|
OFFONE_BYTES ; 11 cycles/1-3 bytes
|
|
ADDLTS count, count, #4
|
|
BEQ OFFONE_EXIT
|
|
CMP count, #2
|
|
STRLTB temp1, [dest], #1
|
|
STRGEH temp1, [dest], #2
|
|
MOVGT temp1, temp1, LSR #16
|
|
STRGTB temp1, [dest], #1
|
|
|
|
OFFONE_EXIT
|
|
|
|
IF Interworking :LOR: Thumbing
|
|
LDMIA sp!, {dest, temp2, temp3, lr}
|
|
BX lr
|
|
ELSE
|
|
LDMIA sp!, {dest, temp2, temp3, pc} ; Return to caller
|
|
ENDIF
|
|
|
|
BYTEMOVE4 ; 12 cycles/4 bytes
|
|
CMP count, #4
|
|
BLT MMOVEXIT
|
|
LDRB temp1, [source], #1
|
|
SUB count, count, #4
|
|
LDRB temp2, [source], #1
|
|
LDRB temp3, [source], #1
|
|
LDRB lr, [source], #1
|
|
STRB temp1, [dest], #1
|
|
STRB temp2, [dest], #1
|
|
STRB temp3, [dest], #1
|
|
STRB lr, [dest], #1
|
|
|
|
MMOVEXIT ; 2-5 cycles
|
|
CMP count, #0
|
|
IF Interworking :LOR: Thumbing
|
|
LDMEQIA sp!, {dest, temp2, temp3, lr}
|
|
BXEQ lr
|
|
ELSE
|
|
LDMEQIA sp!, {dest, temp2, temp3, pc} ; On zero, Return to caller
|
|
ENDIF
|
|
|
|
;
|
|
; Store last 3 or so bytes and exit
|
|
;
|
|
BYTEMOVE ; 4-7 cycles/1 byte
|
|
LDRB temp1, [source], #1
|
|
CMP count, #2
|
|
STRB temp1, [dest], #1
|
|
BLT BYTEMOVE_EXIT
|
|
LDRGEB temp2, [source], #1 ; 8 cycles/1-2 bytes
|
|
LDRGTB temp3, [source], #1
|
|
STRGEB temp2, [dest], #1
|
|
STRGTB temp3, [dest], #1
|
|
|
|
BYTEMOVE_EXIT
|
|
|
|
IF Interworking :LOR: Thumbing
|
|
LDMIA sp!, {dest, temp2, temp3, lr}
|
|
BX lr
|
|
ELSE
|
|
LDMIA sp!, {dest, temp2, temp3, pc} ; Return to caller
|
|
ENDIF
|
|
|
|
ENTRY_END memmove
|
|
|
|
END
|