495 lines
19 KiB
C
495 lines
19 KiB
C
//++
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//
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//Copyright (c) Microsoft Corporation
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//
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//Module Name:
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//
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// blkd1394.h
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//
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//Abstract:
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//
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// This module defines 1394 structures.
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//
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//Environment:
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//
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// Boot loader.
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//
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//--
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//
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// Various OHCI definitions
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//
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#define PHY_INITIATE_BUS_RESET 0x40 // IBR @ Address 1
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///////////////////////////////////////////////////////// Register Structures.
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//
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typedef union _VERSION_REGISTER {
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struct {
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UINT32 Revision:8; // bits 0-7
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UINT32 Reserved:8; // bits 8-15
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UINT32 Version:8; // bits 16-23
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UINT32 GUID_ROM:1; // bit 24
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UINT32 Reserved1:7; // bits 25-31
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};
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UINT32 all;
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} VERSION_REGISTER;
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C_ASSERT(sizeof(VERSION_REGISTER) == 4);
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typedef union _VENDOR_ID_REGISTER {
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struct {
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UINT32 VendorCompanyId:24; // bits 0-23
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UINT32 VendorUnique:8; // bits 24-31
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};
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UINT32 all;
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} VENDOR_ID_REGISTER;
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C_ASSERT(sizeof(VENDOR_ID_REGISTER) == 4);
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typedef union _GUID_ROM_REGISTER {
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struct {
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UINT32 Reserved0:16; // bits 0-15
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UINT32 RdData:8; // bits 16-23
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UINT32 Reserved1:1; // bit 24
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UINT32 RdStart:1; // bit 25
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UINT32 Reserved2:5; // bits 26-30
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UINT32 AddrReset:1; // bits 31
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};
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UINT32 all;
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} GUID_ROM_REGISTER;
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C_ASSERT(sizeof(GUID_ROM_REGISTER) == 4);
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typedef union _AT_RETRIES_REGISTER {
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struct {
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UINT32 MaxATReqRetries:4; // bits 0-3
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UINT32 MaxATRespRetries:4; // bits 4-7
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UINT32 MaxPhysRespRetries:4; // bits 8-11
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UINT32 Reserved:4; // bits 12-15
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UINT32 CycleLimit:13; // bits 16-28
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UINT32 SecondLimit:3; // bits 29-31
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};
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UINT32 all;
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} AT_RETRIES_REGISTER;
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C_ASSERT(sizeof(AT_RETRIES_REGISTER) == 4);
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typedef union _CSR_CONTROL_REGISTER {
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struct {
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UINT32 CsrSel:2; // bits 0-1
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UINT32 Reserved:29; // bits 2-30
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UINT32 CsrDone:1; // bit 31
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};
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UINT32 all;
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} CSR_CONTROL_REGISTER;
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C_ASSERT(sizeof(CSR_CONTROL_REGISTER) == 4);
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typedef union _CONFIG_ROM_HEADER_REGISTER {
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struct {
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UINT32 Rom_crc_value:16; // bits 0-15
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UINT32 Crc_length:8; // bits 16-23
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UINT32 Info_length:8; // bits 24-31
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};
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UINT32 all;
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} CONFIG_ROM_HEADER_REGISTER;
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C_ASSERT(sizeof(CONFIG_ROM_HEADER_REGISTER) == 4);
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typedef union _BUS_OPTIONS_REGISTER {
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struct {
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UINT32 Link_spd:3; // bits 0-2
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UINT32 Reserved0:3; // bits 3-5
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UINT32 g:2; // bits 6-7
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UINT32 Reserved1:4; // bits 8-11
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UINT32 Max_rec:4; // bits 12-15
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UINT32 Cyc_clk_acc:8; // bits 16-23
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UINT32 Reserved2:3; // bits 24-26
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UINT32 Pmc:1; // bit 27
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UINT32 Bmc:1; // bit 28
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UINT32 Isc:1; // bit 29
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UINT32 Cmc:1; // bit 30
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UINT32 Irmc:1; // bit 31
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};
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UINT32 all;
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} BUS_OPTIONS_REGISTER;
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C_ASSERT(sizeof(BUS_OPTIONS_REGISTER) == 4);
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typedef union _HC_CONTROL_REGISTER {
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struct {
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UINT32 Reserved:16; // bits 0-15
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UINT32 SoftReset:1; // bit 16
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UINT32 LinkEnable:1; // bit 17
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UINT32 PostedWriteEnable:1; // bit 18
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UINT32 Lps:1; // bit 19
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UINT32 Reserved2:2; // bits 20-21
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UINT32 APhyEnhanceEnable:1; // bit 22
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UINT32 ProgramPhyEnable:1; // bit 23
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UINT32 Reserved3:6; // bits 24-29
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UINT32 NoByteSwapData:1; // bit 30
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UINT32 Reserved4:1; // bit 31
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};
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UINT32 all;
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} HC_CONTROL_REGISTER;
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C_ASSERT(sizeof(HC_CONTROL_REGISTER) == 4);
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typedef union _FAIRNESS_CONTROL_REGISTER {
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struct {
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UINT32 Pri_req:8; // bits 0-7
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UINT32 Reserved0:24; // bits 8-31
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};
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UINT32 all;
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} FAIRNESS_CONTROL_REGISTER;
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C_ASSERT(sizeof(FAIRNESS_CONTROL_REGISTER) == 4);
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typedef union _LINK_CONTROL_REGISTER {
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struct {
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UINT32 Reserved0:4; // bits 0-3
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UINT32 CycleSyncLReqEnable:1; // bit 4
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UINT32 Reserved1:4; // bits 5-8
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UINT32 RcvSelfId:1; // bit 9
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UINT32 RcvPhyPkt:1; // bit 10
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UINT32 Reserved2:9; // bits 11-19
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UINT32 CycleTimerEnable:1; // bit 20
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UINT32 CycleMaster:1; // bit 21
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UINT32 CycleSource:1; // bit 22
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UINT32 Reserved3:9; // bits 23-31
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};
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UINT32 all;
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} LINK_CONTROL_REGISTER;
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C_ASSERT(sizeof(LINK_CONTROL_REGISTER) == 4);
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typedef union _NODE_ID_REGISTER {
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struct {
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UINT32 NodeId:6; // bits 0-5
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UINT32 BusId:10; // bits 6-15
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UINT32 Reserved1:11; // bits 16-26
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UINT32 Cps:1; // bit 27
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UINT32 Reserved2:2; // bits 28-29
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UINT32 Root:1; // bit 30
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UINT32 IdValid:1; // bit 31
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};
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UINT32 all;
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} NODE_ID_REGISTER;
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C_ASSERT(sizeof(NODE_ID_REGISTER) == 4);
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typedef union _SELF_ID_BUFFER_REGISTER {
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UINT32 SelfIdBufferPointer;
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struct {
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UINT32 Reserved0:11; // bits 0-10
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UINT32 SelfIdBuffer:21; // bits 11-32
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};
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UINT32 all;
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} SELF_ID_BUFFER_REGISTER;
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C_ASSERT(sizeof(SELF_ID_BUFFER_REGISTER) == 4);
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typedef union _SELF_ID_COUNT_REGISTER {
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struct {
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UINT32 Reserved0:2; // bits 0-1
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UINT32 SelfIdSize:11; // bits 2-12
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UINT32 Reserved1:3; // bits 13-15
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UINT32 SelfIdGeneration:8; // bits 16-23
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UINT32 Reserved2:7; // bits 24-30
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UINT32 SelfIdError:1; // bit 31
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};
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UINT32 all;
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} SELF_ID_COUNT_REGISTER;
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C_ASSERT(sizeof(SELF_ID_COUNT_REGISTER) == 4);
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typedef union _PHY_CONTROL_REGISTER {
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struct {
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UINT32 WrData:8; // bits 0-7
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UINT32 RegAddr:4; // bits 8-11
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UINT32 Reserved0:2; // bits 12-13
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UINT32 WrReg:1; // bit 14
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UINT32 RdReg:1; // bit 15
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UINT32 RdData:8; // bits 16-23
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UINT32 RdAddr:4; // bits 24-27
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UINT32 Reserved1:3; // bits 28-30
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UINT32 RdDone:1; // bit 31
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};
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UINT32 all;
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} PHY_CONTROL_REGISTER;
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C_ASSERT(sizeof(PHY_CONTROL_REGISTER) == 4);
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typedef union _ISOCH_CYCLE_TIMER_REGISTER {
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struct {
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UINT32 CycleOffset:12; // bits 0-11
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UINT32 CycleCount:13; // bits 12-24
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UINT32 CycleSeconds:7; // bits 25-31
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};
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UINT32 all;
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} ISOCH_CYCLE_TIMER_REGISTER;
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C_ASSERT(sizeof(ISOCH_CYCLE_TIMER_REGISTER) == 4);
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typedef union _INT_EVENT_MASK_REGISTER {
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struct {
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UINT32 ReqTxComplete:1; // bit 0
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UINT32 RspTxComplete:1; // bit 1
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UINT32 ARRQ:1; // bit 2
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UINT32 ARRS:1; // bit 3
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UINT32 RQPkt:1; // bit 4
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UINT32 RSPPkt:1; // bit 5
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UINT32 IsochTx:1; // bit 6
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UINT32 IsochRx:1; // bit 7
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UINT32 PostedWriteErr:1; // bit 8
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UINT32 LockRespErr:1; // bit 9
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UINT32 Reserved0:6; // bits 10-15
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UINT32 SelfIdComplete:1; // bit 16
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UINT32 BusReset:1; // bit 17
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UINT32 Reserved1:1; // bit 18
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UINT32 Phy:1; // bit 19
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UINT32 CycleSynch:1; // bit 20
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UINT32 Cycle64Secs:1; // bit 21
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UINT32 CycleLost:1; // bit 22
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UINT32 CycleInconsistent:1; // bit 23
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UINT32 UnrecoverableError:1; // bit 24
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UINT32 CycleTooLong:1; // bit 25
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UINT32 PhyRegRcvd:1; // bit 26
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UINT32 Reserved2:3; // bits 27-29
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UINT32 VendorSpecific:1; // bit 30
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UINT32 MasterIntEnable:1; // bit 31
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};
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UINT32 all;
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} INT_EVENT_MASK_REGISTER;
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C_ASSERT(sizeof(INT_EVENT_MASK_REGISTER) == 4);
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typedef union _COMMAND_POINTER_REGISTER {
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struct {
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UINT32 Z:4; // bits 0-3
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UINT32 DescriptorAddr:28; // bits 4-31
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};
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UINT32 all;
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} COMMAND_POINTER_REGISTER;
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C_ASSERT(sizeof(COMMAND_POINTER_REGISTER) == 4);
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typedef union _CONTEXT_CONTROL_REGISTER {
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struct {
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UINT32 EventCode:5; // bits 0-4
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UINT32 Spd:3; // bits 5-7
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UINT32 Reserved0:2; // bits 8-9
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UINT32 Active:1; // bit 10
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UINT32 Dead:1; // bit 11
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UINT32 Wake:1; // bit 12
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UINT32 Reserved1:2; // bits 13-14
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UINT32 Run:1; // bit 15
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UINT32 Reserved2:16; // bits 16-31
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};
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UINT32 all;
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} CONTEXT_CONTROL_REGISTER;
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C_ASSERT(sizeof(CONTEXT_CONTROL_REGISTER) == 4);
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typedef union _IT_CONTEXT_CONTROL_REGISTER {
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struct {
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UINT32 EventCode:5; // bits 0-4
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UINT32 Spd:3; // bits 5-7
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UINT32 Reserved0:2; // bits 8-9
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UINT32 Active:1; // bit 10
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UINT32 Dead:1; // bit 11
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UINT32 Wake:1; // bit 12
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UINT32 Reserved1:2; // bits 13-14
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UINT32 Run:1; // bit 15
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UINT32 CycleMatch:15; // bits 16-30
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UINT32 CycleMatchEnable:1; // bit 31
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};
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UINT32 all;
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} IT_CONTEXT_CONTROL_REGISTER;
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C_ASSERT(sizeof(IT_CONTEXT_CONTROL_REGISTER) == 4);
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typedef union _IR_CONTEXT_CONTROL_REGISTER {
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struct {
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UINT32 EventCode:5; // bits 0-4
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UINT32 Spd:3; // bits 5-7
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UINT32 Reserved0:2; // bits 8-9
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UINT32 Active:1; // bit 10
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UINT32 Dead:1; // bit 11
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UINT32 Wake:1; // bit 12
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UINT32 Reserved1:2; // bits 13-14
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UINT32 Run:1; // bit 15
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UINT32 CycleMatch:12; // bits 16-27
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UINT32 MultiChanMode:1; // bit 28
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UINT32 CycleMatchEnable:1; // bit 29
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UINT32 IsochHeader:1; // bit 30
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UINT32 BufferFill:1; // bit 31
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};
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UINT32 all;
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} IR_CONTEXT_CONTROL_REGISTER;
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C_ASSERT(sizeof(IR_CONTEXT_CONTROL_REGISTER) == 4);
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typedef union _CONTEXT_MATCH_REGISTER {
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struct {
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UINT32 ChannelNumber:6; // bits 0-5
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UINT32 Reserved:1; // bit 6
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UINT32 Tag1SyncFilter:1; // bit 7
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UINT32 Sync:4; // bits 8-11
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UINT32 CycleMatch:13; // bits 12-24
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UINT32 Reserved1:3; // bits 25-27
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UINT32 Tag:4; // bit 28-31
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};
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UINT32 all;
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} CONTEXT_MATCH_REGISTER;
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C_ASSERT(sizeof(CONTEXT_MATCH_REGISTER) == 4);
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/////////////////////////////////////////////////////////////// Register Sets.
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//
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typedef struct _DMA_CONTEXT_REGISTERS {
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CONTEXT_CONTROL_REGISTER ContextControlSet;
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CONTEXT_CONTROL_REGISTER ContextControlClear;
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UINT32 Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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UINT32 Reserved1[4];
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} DMA_CONTEXT_REGISTERS;
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typedef struct _DMA_ISOCH_RCV_CONTEXT_REGISTERS {
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IR_CONTEXT_CONTROL_REGISTER ContextControlSet;
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IR_CONTEXT_CONTROL_REGISTER ContextControlClear;
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UINT32 Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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CONTEXT_MATCH_REGISTER ContextMatch;
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UINT32 Reserved1[3];
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} DMA_ISOCH_RCV_CONTEXT_REGISTERS;
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typedef struct _DMA_ISOCH_XMIT_CONTEXT_REGISTERS {
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IT_CONTEXT_CONTROL_REGISTER ContextControlSet;
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IT_CONTEXT_CONTROL_REGISTER ContextControlClear;
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UINT32 Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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} DMA_ISOCH_XMIT_CONTEXT_REGISTERS;
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typedef struct _OHCI_REGISTER_MAP {
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VERSION_REGISTER Version; // @ 0
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GUID_ROM_REGISTER GUID_ROM; // @ 4
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AT_RETRIES_REGISTER ATRetries; // @ 8
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UINT32 CsrData; // @ C
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UINT32 CsrCompare; // @ 10
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CSR_CONTROL_REGISTER CsrControl; // @ 14
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CONFIG_ROM_HEADER_REGISTER ConfigRomHeader; // @ 18
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UINT32 BusId; // @ 1C
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BUS_OPTIONS_REGISTER BusOptions; // @ 20
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UINT32 GuidHi; // @ 24
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UINT32 GuidLo; // @ 28
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UINT32 Reserved0[2]; // @ 2C
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UINT32 ConfigRomMap; // @ 34
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UINT32 PostedWriteAddressLo; // @ 38
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UINT32 PostedWriteAddressHi; // @ 3C
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VENDOR_ID_REGISTER VendorId; // @ 40
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UINT32 Reserved1[3]; // @ 44
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HC_CONTROL_REGISTER HCControlSet; // @ 50
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HC_CONTROL_REGISTER HCControlClear; // @ 54
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UINT32 Reserved2[3]; // @ 58
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SELF_ID_BUFFER_REGISTER SelfIdBufferPtr; // @ 64
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SELF_ID_COUNT_REGISTER SelfIdCount; // @ 68
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UINT32 Reserved3[1]; // @ 6C
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UINT32 IRChannelMaskHiSet; // @ 70
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UINT32 IRChannelMaskHiClear; // @ 74
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UINT32 IRChannelMaskLoSet; // @ 78
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UINT32 IRChannelMaskLoClear; // @ 7C
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INT_EVENT_MASK_REGISTER IntEventSet; // @ 80
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INT_EVENT_MASK_REGISTER IntEventClear; // @ 84
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INT_EVENT_MASK_REGISTER IntMaskSet; // @ 88
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INT_EVENT_MASK_REGISTER IntMaskClear; // @ 8C
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UINT32 IsoXmitIntEventSet; // @ 90
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UINT32 IsoXmitIntEventClear; // @ 94
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UINT32 IsoXmitIntMaskSet; // @ 98
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UINT32 IsoXmitIntMaskClear; // @ 9C
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UINT32 IsoRecvIntEventSet; // @ A0
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UINT32 IsoRecvIntEventClear; // @ A4
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UINT32 IsoRecvIntMaskSet; // @ A8
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UINT32 IsoRecvIntMaskClear; // @ AC
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UINT32 Reserved4[11]; // @ B0
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FAIRNESS_CONTROL_REGISTER FairnessControl; // @ DC
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LINK_CONTROL_REGISTER LinkControlSet; // @ E0
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LINK_CONTROL_REGISTER LinkControlClear; // @ E4
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NODE_ID_REGISTER NodeId; // @ E8
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PHY_CONTROL_REGISTER PhyControl; // @ EC
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ISOCH_CYCLE_TIMER_REGISTER IsochCycleTimer; // @ F0
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UINT32 Reserved5[3]; // @ F4
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UINT32 AsynchReqFilterHiSet; // @ 100
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UINT32 AsynchReqFilterHiClear; // @ 104
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UINT32 AsynchReqFilterLoSet; // @ 108
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UINT32 AsynchReqFilterLoClear; // @ 10C
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UINT32 PhyReqFilterHiSet; // @ 110
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UINT32 PhyReqFilterHiClear; // @ 114
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UINT32 PhyReqFilterLoSet; // @ 118
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UINT32 PhyReqFilterLoClear; // @ 11C
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UINT32 PhysicalUpperBound; // @ 120
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UINT32 Reserved6[23]; // @ 124
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DMA_CONTEXT_REGISTERS AsynchContext[4]; // @ 180
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// ATRsp_Context; // @ 1A0
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// ARReq_Context; // @ 1C0
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// ARRsp_Context; // @ 1E0
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DMA_ISOCH_XMIT_CONTEXT_REGISTERS IT_Context[32]; // @ 200
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DMA_ISOCH_RCV_CONTEXT_REGISTERS IR_Context[32]; // @ 400
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} OHCI_REGISTER_MAP;
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C_ASSERT(sizeof(OHCI_REGISTER_MAP) == 2048);
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//
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// IEEE 1212 Configuration Rom header definition
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//
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typedef union _CONFIG_ROM_INFO {
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struct {
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union {
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UINT16 CRI_CRC_Value:16;
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struct {
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UINT8 CRI_Saved_Info_Length;
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UINT8 CRI_Saved_CRC_Length;
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} Saved;
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};
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UINT8 CRI_CRC_Length;
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UINT8 CRI_Info_Length;
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};
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UINT32 all;
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} CONFIG_ROM_INFO;
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C_ASSERT(sizeof(CONFIG_ROM_INFO) == 4);
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//
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// IEEE 1212 Immediate entry definition
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//
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typedef union _IMMEDIATE_ENTRY {
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struct {
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UINT32 IE_Value:24;
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UINT32 IE_Key:8;
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};
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UINT32 all;
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} IMMEDIATE_ENTRY;
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C_ASSERT(sizeof(IMMEDIATE_ENTRY) == 4);
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//
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// IEEE 1212 Directory definition
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//
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typedef union _DIRECTORY_INFO {
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struct {
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union {
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UINT16 DI_CRC;
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UINT16 DI_Saved_Length;
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};
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UINT16 DI_Length;
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};
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UINT32 all;
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} DIRECTORY_INFO;
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C_ASSERT(sizeof(DIRECTORY_INFO) == 4);
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//
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///////////////////////////////////////////////////////////////// End of File.
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