901 lines
33 KiB
Plaintext
901 lines
33 KiB
Plaintext
///////////////////////////////////////////////////////////////////////////////
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//
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// Microsoft Research Singularity
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// File: Tulip.cs
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//
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// Simple Driver for DEC 21140a PCI Ethernet card. (as used in Virtual PC)
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//
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// Useful reference URLs:
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// http://www.intel.com/design/network/manuals/21140ahm.pdf
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//
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// TODO:
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// - MII support
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// - Loss of Carrier / No Carrier Handling
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// - Promiscuous mode switching
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// - Filtering
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// - Receive Watchdog / Jabber Handling
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// - Event Counters
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// - Review why is this driver using I/O ports.
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//
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// NB: This code is only tested on Virtual PC 2007 and would probably have
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// error handling issues on real hardware.
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using System;
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using System.Threading;
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using System.Diagnostics;
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using System.Collections;
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using Microsoft.Singularity.Channels;
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using Microsoft.Singularity.Io;
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using Microsoft.Singularity.Configuration;
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using Microsoft.Singularity.Io.Net;
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using Microsoft.Singularity.V1.Services;
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using Drivers.Net;
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using Microsoft.Singularity.Drivers;
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namespace Microsoft.Singularity.Drivers.Network.Tulip
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{
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internal class Tulip
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{
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internal const uint MaxRxPackets = 512;
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internal const uint MaxTxPackets = 512;
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internal const uint MaxRxFragmentsPerPacket = 1;
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internal const uint MaxTxFragmentsPerPacket = 8;
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internal const uint MaxRxFragmentsInRing = MaxRxPackets * MaxRxFragmentsPerPacket;
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internal const uint MaxTxFragmentsInRing = MaxTxPackets * MaxTxFragmentsPerPacket;
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internal const uint MtuBytes = 1514;
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internal const uint SetupFrameBytes = 192;
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private const uint BytesPerDescriptor = 16;
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// MAC address
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private EthernetAddress macAddress;
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private uint unit;
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// State for tracking controllers sharing serial rom
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private static EthernetAddress macBase;
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private static uint lastUnit = 0;
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// PCI stuff
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private PciDeviceConfig! config;
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// CSRs
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private IoPort! csr0;
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private IoPort! csr1;
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private IoPort! csr2;
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private IoPort! csr3;
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private IoPort! csr4;
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private IoPort! csr5;
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private IoPort! csr6;
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private IoPort! csr7;
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private IoPort! csr8;
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private IoPort! csr9;
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private IoPort! csr10;
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private IoPort! csr11;
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private IoPort! csr12;
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private IoPort! csr15;
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private IoIrq! irq;
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private TulipTxRingBuffer! txRing;
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private TulipRxRingBuffer! rxRing;
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private EthernetAddress ethernetAddress;
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private TulipEventRelay eventRelay;
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private Thread irqWorker;
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private volatile uint irqLastStatus;
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private volatile bool irqWorkerStop;
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private volatile bool isShutdown = false;
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// Constructor
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internal Tulip(TulipResources! res)
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{
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TulipDebug.Print("Tulip: Initialize() called\n");
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assume res.csr != null;
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assume res.irq != null;
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csr0 = (!)res.csr.PortAtOffset(0x00, 4, Access.ReadWrite);
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csr1 = (!)res.csr.PortAtOffset(0x08, 4, Access.Write);
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csr2 = (!)res.csr.PortAtOffset(0x10, 4, Access.Write);
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csr3 = (!)res.csr.PortAtOffset(0x18, 4, Access.ReadWrite);
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csr4 = (!)res.csr.PortAtOffset(0x20, 4, Access.ReadWrite);
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csr5 = (!)res.csr.PortAtOffset(0x28, 4, Access.ReadWrite);
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csr6 = (!)res.csr.PortAtOffset(0x30, 4, Access.ReadWrite);
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csr7 = (!)res.csr.PortAtOffset(0x38, 4, Access.ReadWrite);
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csr8 = (!)res.csr.PortAtOffset(0x40, 4, Access.Read);
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csr9 = (!)res.csr.PortAtOffset(0x48, 4, Access.ReadWrite);
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csr10 = (!)res.csr.PortAtOffset(0x50, 4, Access.Read);
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csr11 = (!)res.csr.PortAtOffset(0x58, 4, Access.ReadWrite);
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csr12 = (!)res.csr.PortAtOffset(0x60, 4, Access.ReadWrite);
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csr15 = (!)res.csr.PortAtOffset(0x78, 4, Access.ReadWrite);
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irq = (!)res.irq.IrqAtOffset(0);
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TulipDebug.Print("Tulip IRQ {0}\n", __arglist(res.irq.ToString()));
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PciDeviceConfig! config = this.config = (PciDeviceConfig!)IoConfig.GetConfig();
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Debug.Assert((config.InterruptsEnabled));
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this.txRing = new TulipTxRingBuffer(MaxTxPackets,
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MaxTxFragmentsInRing);
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this.rxRing = new TulipRxRingBuffer(MaxRxFragmentsInRing);
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}
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internal void StartIo()
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{
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Debug.Assert(irqWorker == null);
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TulipDebug.Print("StartIo\n");
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if (isShutdown) {
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return;
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}
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csr6.Write32(CSR6.MBO | CSR6.HBD | CSR6.PS | (3u << CSR6.TR_ROLL) |
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CSR6.ST);
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WriteStandardSetupFrame();
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// Write CSR6 to start receive and transmit processes
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//
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// This is taken from the state remaining after pxeboot.
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// == 100Mb/s MII/SYM (table 3-43 entry 1000)
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csr6.Write32(CSR6.MBO | CSR6.HBD | CSR6.PS | (3u << CSR6.TR_ROLL) |
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CSR6.ST | CSR6.SR);
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TulipDebug.Print("Programmed CSR values...\n");
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TulipDebug.PrintCsrs(csr0, csr1, csr2, csr3, csr4, csr5, csr6,
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csr7, csr8, csr9, csr10, csr11, csr12, csr15);
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TulipDebug.Print("CFCS: {0:x4} {1:x4}\n",
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__arglist(config.Control, config.Status));
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irqWorkerStop = false;
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irqWorker = new Thread(new ThreadStart(this.IrqWorkerMain));
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irqWorker.Start();
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}
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internal void StopIo()
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{
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if (irqWorker != null) {
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// Set stop flag, wake-up irqWorker thread, then wait.
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irqWorkerStop = true;
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irq.Pulse();
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irqWorker.Join();
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irqWorker = null;
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}
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}
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internal void Shutdown()
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{
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isShutdown = true;
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StopIo();
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}
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public bool IsShutdown { get { return isShutdown; } }
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private void InitChains()
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{
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TulipDebug.Print("InitChains(rx = {0}, tx = {1})\n",
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__arglist(MaxRxFragmentsInRing,
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MaxTxFragmentsInRing));
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// Turn off receive and transmit
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uint mode = csr6.Read32();
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mode &= ~(CSR6.SR | CSR6.ST);
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csr6.Write32(mode);
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this.rxRing.Reset();
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csr3.Write32(this.rxRing.BaseAddress.ToUInt32());
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this.txRing.Reset();
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csr4.Write32(this.txRing.BaseAddress.ToUInt32());
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}
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// Device methods
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internal void Initialize()
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{
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TulipDebug.Print("Tulip: Initialize() called\n");
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// Dump config registers
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TulipDebug.Print("Initial CSR values...\n");
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TulipDebug.PrintCsrs(csr0, csr1, csr2, csr3, csr4, csr5, csr6,
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csr7, csr8, csr9, csr10, csr11, csr12, csr15);
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// Perform reset to clear out any state we may have left over
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// from pxeboot.
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csr0.Write32(CSR0.SWR);
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TulipDebug.Print("Reset and new CSR values...\n");
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TulipDebug.PrintCsrs(csr0, csr1, csr2, csr3, csr4, csr5, csr6,
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csr7, csr8, csr9, csr10, csr11, csr12, csr15);
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// Pull Serial Rom and parse data
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byte[]! srom = PullSRom();
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TulipDebug.PrintBytes("SROM", srom);
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// Assign mac address. Note we may have multiple
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// phy's sharing the same rom and multiple cards and
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// the below is not foolproof.
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EthernetAddress macRom = EthernetAddress.ParseBytes(srom, 20);
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if (macBase != macRom) {
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macBase = macRom;
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unit = 0;
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} else {
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unit = lastUnit + 1;
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}
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macAddress = macRom;
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for (int i = 1; i < unit; i++) {
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macAddress++;
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}
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lastUnit = unit;
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// Register Interrupt
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if (irq.RegisterInterrupt() == false) {
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DebugStub.Break();
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}
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// Figure out PCI cache bits for csr0
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// Not sure this is sane.
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uint cls = config.CacheLineSize;
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uint cacheBits = CSR0.WIE | CSR0.RLE | CSR0.RME;
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if (cls < 8 || cls > 32) {
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cls = 0;
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cacheBits = 0;
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}
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InitChains();
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// Write CSR0 to set global host bus operating parameters
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csr0.Write32(cacheBits | CSR0.BAR |
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((cls / 8u) << CSR0.CAL_ROLL) |
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(cls << CSR0.PBL_ROLL));
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// This is a debug helper and could be used to switch to
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// polling mode.
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//
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StartPeriodicTimer(TimeSpan.FromMilliseconds(1000));
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// And remember to enable the timer interrupt below CSR7.GPT
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// Write CSR7 to mask unnecessary interrupts
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csr7.Write32(CSR7.AI | CSR7.RI | CSR7.TI | CSR7.GPT);
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}
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internal void Finalize()
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{
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irq.ReleaseInterrupt();
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// Get worker thread to end main loop. When it terminates
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irqWorkerStop = true;
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TulipDebug.Print("Tulip: Finalize() called\n");
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}
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internal string! Name
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{
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get { return "DE2114x Ethernet"; }
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}
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internal string! Version
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{
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get { return "0.1"; }
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}
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internal EthernetAddress HardwareAddress
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{
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get { return macAddress; }
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}
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internal byte[]! HardwareAddressBytes
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{
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get {
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byte [] tmp = macAddress.GetAddressBytes();
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if (tmp != null) return tmp;
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return new byte[6] { 0, 0, 0, 0, 0, 0 };
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}
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}
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internal uint LinkSpeed
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{
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get { return 10 * 1000 * 1000; }
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}
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internal EthernetAddress BssId
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{
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get { return EthernetAddress.Zero; }
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}
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private void ReceivePollDemand()
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{
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csr2.Write32(1);
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}
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internal void GetReceivedPackets(PacketFifo*! in ExHeap fifo)
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{
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rxRing.Pop(fifo);
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// ReceivePollDemand();
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}
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internal void ReceivePackets(PacketFifo*! in ExHeap fifo)
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ensures fifo->Count == 0;
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{
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rxRing.Push(fifo);
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ReceivePollDemand();
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}
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private void TransmitPollDemand()
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{
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csr1.Write32(1);
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}
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internal void GetTransmittedPackets(PacketFifo*! in ExHeap fifo)
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{
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txRing.Pop(fifo);
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TransmitPollDemand();
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}
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internal void TransmitPackets(PacketFifo*! in ExHeap fifo)
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ensures fifo->Count == 0;
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{
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txRing.Push(fifo);
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TransmitPollDemand();
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}
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//
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// IrqWorker thread and related event notification setter
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//
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internal void SetEventRelay(TulipEventRelay theEventRelay)
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{
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eventRelay = theEventRelay;
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}
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private void StartPeriodicTimer(TimeSpan period)
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{
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long ticksPerBit;
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uint mode = csr6.Read32();
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if ((mode & (CSR6.PS | CSR6.TTM)) != 0) {
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// 10 MB port
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ticksPerBit = 2048;
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} else if ((mode & (CSR6.PS | CSR6.TTM | CSR6.PCS | CSR6.SCR)) ==
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(CSR6.PS | CSR6.TTM)) {
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// 10 MB MII/SYM
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ticksPerBit = 8192;
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} else {
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// 100 MB
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ticksPerBit = 819;
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}
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long bv = period.Ticks / ticksPerBit;
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if (bv > 0xffff)
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bv = 0xffff;
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csr11.Write32(0x10000 | (uint)bv);
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}
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private void IrqWorkerMain()
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{
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Tracing.Log(Tracing.Debug, "Start worker thread.");
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// Grab IoPorts used locally from instance so other threads
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// can not use them.
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while (irqWorkerStop == false) {
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uint status = 0;
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while (status == 0) {
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irq.WaitForInterrupt();
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status = csr5.Read32() & CSR5.VALID;
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}
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DumpCsr5(status);
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rxRing.DumpOwnership("Interrupt");
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uint tulipEvent = TulipEvent.NoEvent;
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if ((status & (CSR5.EB|CSR5.FBE)) != 0) {
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TulipDebug.Print("Error: csr5.EB = {0} csr5.FBE = {1}\n",
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__arglist(status & CSR5.EB, status & CSR5.FBE));
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DebugStub.Break();
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}
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if ((status & CSR5.RWT) != 0) {
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}
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if ((status & CSR5.TJT) != 0) {
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}
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if ((status & CSR5.AIS) != 0) {
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txRing.ClearTransmitError();
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TransmitPollDemand();
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}
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if ((status & (CSR5.RI | CSR5.RPS)) != 0) {
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tulipEvent |= TulipEvent.ReceiveEvent;
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}
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if ((status & CSR5.TI) != 0) {
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tulipEvent |= TulipEvent.TransmitEvent;
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}
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// Clear status bits
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csr5.Write32(status);
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// Enable interrupts
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// csr7.Write32(CSR7.AI | CSR7.RI | CSR7.TI );
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// Acknowledge Interrupt
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irq.AckInterrupt();
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// Announce events
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if (eventRelay != null) {
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eventRelay.ForwardEvent(tulipEvent);
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}
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}
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// Perform software reset to stop processing
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csr0.Write32(CSR0.SWR);
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TulipDebug.Print("Tulip Stopped.");
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}
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[ System.Diagnostics.Conditional("DEBUG_TULIP") ]
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private static void DumpCsr5(uint v)
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{
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v &= CSR5.VALID;
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TulipDebug.Print("CSR5 : {0:x8} ", __arglist(v));
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uint eb = (v >> CSR5.EB_ROLL) & CSR5.EB_MASK;
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if ((v & CSR5.FBE) != 0) {
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TulipDebug.Print("Fatal bus error: {0}\n", __arglist(eb));
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return;
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}
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uint ts = (v >> CSR5.TS_ROLL) & CSR5.TS_MASK;
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switch (ts) {
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case 0: TulipDebug.Print("TS - STOPPED "); break;
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case 1: TulipDebug.Print("TS - RUN (Fetch) "); break;
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case 2: TulipDebug.Print("TS - RUN (Wait) "); break;
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case 3: TulipDebug.Print("TS - RUN (Fifo) "); break;
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case 4: TulipDebug.Print("TS - RESERVED "); break;
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case 5: TulipDebug.Print("TS - RUN (Setup) "); break;
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case 6: TulipDebug.Print("TS - Suspended "); break;
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case 7: TulipDebug.Print("TS - RUN (Close) "); break;
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}
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uint rs = (v >> CSR5.RS_ROLL) & CSR5.RS_MASK;
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switch (rs) {
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case 0: TulipDebug.Print("RS - STOPPED "); break;
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case 1: TulipDebug.Print("RS - RUN (Fetch) "); break;
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case 2: TulipDebug.Print("RS - RUN (Check) "); break;
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case 3: TulipDebug.Print("RS - RUN (Wait) "); break;
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case 4: TulipDebug.Print("RS - Suspended ) "); break;
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case 5: TulipDebug.Print("RS - RUN (Close) "); break;
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case 6: TulipDebug.Print("RS - RUN (Flush) "); break;
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case 7: TulipDebug.Print("RS - RUN (Queue) "); break;
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}
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if ((v & CSR5.NIS) != 0) TulipDebug.Print("NIS ");
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if ((v & CSR5.AIS) != 0) TulipDebug.Print("AIS ");
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if ((v & CSR5.ERI) != 0) TulipDebug.Print("ERI ");
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if ((v & CSR5.FBE) != 0) TulipDebug.Print("FBE ");
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if ((v & CSR5.GTE) != 0) TulipDebug.Print("GTE ");
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if ((v & CSR5.ETI) != 0) TulipDebug.Print("ETI ");
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if ((v & CSR5.RWT) != 0) TulipDebug.Print("RWT ");
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if ((v & CSR5.RPS) != 0) TulipDebug.Print("RPS ");
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if ((v & CSR5.RU) != 0) TulipDebug.Print("RU ");
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if ((v & CSR5.RI) != 0) TulipDebug.Print("RI ");
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if ((v & CSR5.UNF) != 0) TulipDebug.Print("UNF ");
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if ((v & CSR5.TJT) != 0) TulipDebug.Print("TJT ");
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if ((v & CSR5.TU) != 0) TulipDebug.Print("TU ");
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if ((v & CSR5.TPS) != 0) TulipDebug.Print("TPS ");
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if ((v & CSR5.TI) != 0) TulipDebug.Print("TI ");
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TulipDebug.Print("\n");
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}
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//
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// SROM related methods
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//
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private uint GetSRomAddressWidth()
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{
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for (uint i = 6; i < 13; i++) {
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ushort w = SRomRead16(18u, i);
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if (w == 0) {
|
||
return i - 1;
|
||
}
|
||
}
|
||
return 6;
|
||
}
|
||
|
||
private byte[]! PullSRom()
|
||
{
|
||
uint sromWidth = GetSRomAddressWidth();
|
||
|
||
byte[] b = new byte[2 << (int)sromWidth];
|
||
|
||
for (uint i = 0; i < b.Length; i += 2) {
|
||
ushort w = SRomRead16(i, sromWidth);
|
||
b[i] = (byte) (w >> 8);
|
||
b[i + 1] = (byte) (w & 0xff);
|
||
}
|
||
return b;
|
||
}
|
||
|
||
[System.Diagnostics.Conditional("HAVE_DELAY")]
|
||
private static void Delay(int kernelTicks)
|
||
{
|
||
long expiry = ProcessService.GetUpTime().Ticks + kernelTicks;
|
||
while (ProcessService.GetUpTime().Ticks < expiry) {
|
||
Thread.Yield();
|
||
}
|
||
}
|
||
|
||
// --------------------------------------------------------------------
|
||
// MII (Based on IEEE802.3-2002 and unreviewed *and* untested).
|
||
|
||
private int MiiReadBit()
|
||
{
|
||
int result = (csr9.Read32() & CSR9.MDI) != 0 ? 1 : 0;
|
||
|
||
csr9.Write32(CSR9.MII); Delay(1);
|
||
csr9.Write32(CSR9.MII | CSR9.MDC); Delay(1);
|
||
csr9.Write32(CSR9.MII); Delay(1);
|
||
return result;
|
||
}
|
||
|
||
private int MiiReadBits(int count)
|
||
{
|
||
int result = 0;
|
||
while (count-- > 0) {
|
||
result = result << 1;
|
||
result |= MiiReadBit();
|
||
}
|
||
return result;
|
||
}
|
||
|
||
private int MiiRead(int phy, int register)
|
||
requires phy <= 31;
|
||
requires register <= 31;
|
||
{
|
||
MiiWriteBits(-1, 32); // Preamble
|
||
// 14 bit write, 18bit read
|
||
MiiWriteBits((6 << 10) | // Start read transaction (2 bits)
|
||
(phy << 5) | // Phy Address (5 bits)
|
||
register, 14); // Register (5 bits)
|
||
int value = MiiReadBits(18);
|
||
MiiWriteBits(0, 32); // Idle
|
||
return value & 0xffff;
|
||
}
|
||
|
||
private void MiiWriteBit(int bit)
|
||
requires bit == 0 || bit == 1;
|
||
{
|
||
uint data = (uint)(bit * CSR9.MDO);
|
||
csr9.Write32(data); Delay(1);
|
||
csr9.Write32(data | CSR9.MDC); Delay(1);
|
||
csr9.Write32(data); Delay(1);
|
||
}
|
||
|
||
// Write count bits from vector to MII
|
||
private void MiiWriteBits(int vector, int count)
|
||
requires count >= 0 && count <= 32;
|
||
{
|
||
while (count-- > 0) {
|
||
MiiWriteBit(vector & 1);
|
||
vector >>= 1;
|
||
}
|
||
}
|
||
|
||
private void MiiWrite(int phy, int register, int value)
|
||
requires phy <= 31;
|
||
requires register <= 31;
|
||
requires value <= 0xffff;
|
||
{
|
||
MiiWriteBits(-1, 32); // Preamble
|
||
MiiWriteBits((0x5 << 28) | // Start write transaction (4 bits)
|
||
(phy << 23) | // Phy Address (5 bits)
|
||
(register << 18) | // Register (5 bits)
|
||
(2 << 16) | // Turnaround 2 cycles (2 bits)
|
||
value, 32);
|
||
MiiWriteBits(0, 32); // Idle
|
||
}
|
||
|
||
// --------------------------------------------------------------------
|
||
// SROM
|
||
|
||
private static ushort CalculateSromCrc(byte[]! srom)
|
||
requires srom.Length > 126;
|
||
{
|
||
// Cut-paste-and-converted directly from SROM 4.09 spec
|
||
const uint POLY = 0x04C11DB6;
|
||
const uint DATA_LEN = 126;
|
||
|
||
uint crc = 0xffffffff;
|
||
|
||
for (uint index = 0; index < DATA_LEN; index++)
|
||
{
|
||
byte currentByte = srom[index];
|
||
for (uint bit = 0; bit < 8; bit++) {
|
||
uint Msb = (crc >> 31) & 1;
|
||
crc <<= 1;
|
||
if ((Msb ^ (currentByte & 1)) != 0) {
|
||
crc ^= POLY;
|
||
crc |= 0x00000001;
|
||
}
|
||
currentByte >>= 1;
|
||
}
|
||
}
|
||
|
||
uint flippedCrc = 0;
|
||
for (uint i = 0; i < 32; i++) {
|
||
flippedCrc <<= 1;
|
||
uint bit = crc & 1;
|
||
crc >>= 1;
|
||
flippedCrc += bit;
|
||
}
|
||
crc = flippedCrc ^ 0xffffffff;
|
||
return (ushort)(crc & 0xffff);
|
||
}
|
||
|
||
private static int DumpLeafMedia(byte[]! srom, int offset)
|
||
{
|
||
if ((0x80 & (int)srom[offset]) == 0) {
|
||
TulipDebug.Print("-- Compact format (non-MII)");
|
||
TulipDebug.Print(" Media code {0:x2} GPR {1:x2} Command {2:x2}{3:x2}\n",
|
||
__arglist(0x3f & (int)srom[offset],
|
||
srom[offset + 1],
|
||
srom[offset + 3],
|
||
srom[offset + 2]));
|
||
return 4;
|
||
}
|
||
else {
|
||
int length = (0x7f & (int)srom[offset]) + 1;
|
||
int type = (int)srom[offset + 1];
|
||
TulipDebug.Print("--- Extended format (Type {0} Length {1})\n",
|
||
__arglist(type, length));
|
||
|
||
if (type == 0x01) {
|
||
int gprLength = (int)srom[offset + 3];
|
||
int resetLength = (int)srom[offset + 4 + gprLength];
|
||
TulipDebug.Print(" MII PHY id = {0:x2} SeqLen {1} ResetLen {2} ",
|
||
__arglist(srom[offset + 2],
|
||
gprLength, resetLength));
|
||
int mediaCaps = ((int)srom[offset + 6 + gprLength + resetLength]) * 256 + (int)srom[offset + 5 + gprLength + resetLength];
|
||
int nWay = ((int)srom[offset + 8 + gprLength + resetLength]) * 256 + (int)srom[offset + 7 + gprLength + resetLength];
|
||
int fdx = ((int)srom[offset + 10 + gprLength + resetLength]) * 256 + (int)srom[offset + 9 + gprLength + resetLength];
|
||
int ttm = ((int)srom[offset + 12 + gprLength + resetLength]) * 256 + (int)srom[offset + 11 + gprLength + resetLength];
|
||
TulipDebug.Print("mediaCaps {0:x4} nWay {1:x4} fdx {2:x4} ttm {3:x4}\n", __arglist(mediaCaps, nWay, fdx, ttm));
|
||
}
|
||
return length;
|
||
}
|
||
}
|
||
|
||
private static void DumpLeafNode(byte[]! srom, int offset)
|
||
{
|
||
TulipDebug.Print("Leaf:\n");
|
||
TulipDebug.Print("- ConnectionType: {0:x2}{1:x2} GPR: {2:x2} InfoBlocks: {3}\n",
|
||
__arglist(srom[offset + 1], srom[offset],
|
||
srom[offset + 2], srom[offset + 3]));
|
||
|
||
int infoBlocks = (int)srom[offset + 3];
|
||
offset += 4;
|
||
for (int i = 0; i < infoBlocks; i++) {
|
||
offset += DumpLeafMedia(srom, offset);
|
||
}
|
||
}
|
||
|
||
private static void DecodeSRom(byte[]! srom)
|
||
{
|
||
TulipDebug.Print("SROM ID Block: Vendor {0:x2}{1:x2} Subsystem {2:x2}{3:x2} HwOpts {4:x2} Func0Opts {5:x2} CRC {6:x2}",
|
||
__arglist(srom[1], srom[0], srom[3], srom[4],
|
||
srom[15], srom[17], srom[16]));
|
||
|
||
TulipDebug.Print("\nSROM Format: {0}\nController Count: {1}",
|
||
__arglist(srom[18], srom[19]));
|
||
|
||
int controllers = (int)srom[19];
|
||
TulipDebug.Print("\nMAC address: {0:x2}:{1:x2}:{2:x2}:{3:x2}:{4:x2}:{5:x2}",
|
||
__arglist(srom[20], srom[21], srom[22],
|
||
srom[23], srom[24], srom[25])
|
||
);
|
||
|
||
for (int i = 0; i < controllers; i++) {
|
||
int offset = 27 + i * 2;
|
||
TulipDebug.Print("\nController {0} leaf offset {1:x2}{2:x2}\n",
|
||
__arglist(i,
|
||
srom[offset + 1], srom[offset])
|
||
);
|
||
DumpLeafNode(srom,
|
||
((int)(srom[offset + 1]) << 8) |
|
||
(int)(srom[offset]));
|
||
}
|
||
}
|
||
|
||
private static byte [] SRomReadPreamble = {
|
||
0x01, 0x31, 0x57, 0x57, 0x51, 0x31
|
||
};
|
||
|
||
private ushort SRomRead16(uint addr, uint addrBits)
|
||
{
|
||
// This is taken from section 7-8 in 21140A reference manual. We
|
||
// deliberately make all delays as 3 ticks since we don't have
|
||
// sufficient resolution and don't care about 300ns vs 150ns for
|
||
// the SROM accesses.
|
||
|
||
const uint srom_base_cmd = 0x4800;
|
||
|
||
// Starting byte address to starting word address
|
||
addr >>= 1;
|
||
|
||
foreach (byte b in SRomReadPreamble)
|
||
{
|
||
csr9.Write32(srom_base_cmd | (uint)(b >> 4)); Delay(3);
|
||
csr9.Write32(srom_base_cmd | (uint)(b & 0x0f)); Delay(3);
|
||
}
|
||
|
||
// Write address to be read
|
||
for (int i = (int)addrBits - 1; i >= 0; --i) {
|
||
uint bit = ((uint)addr >> i) & 0x01;
|
||
bit <<= 2;
|
||
csr9.Write32(srom_base_cmd | bit | 0x01); Delay(3);
|
||
csr9.Write32(srom_base_cmd | bit | 0x03); Delay(3);
|
||
csr9.Write32(srom_base_cmd | bit | 0x01); Delay(3);
|
||
}
|
||
|
||
// Get lsb
|
||
uint r = 0;
|
||
for (int i = 7; i >= 0; --i) {
|
||
csr9.Write32(srom_base_cmd | 0x03); Delay(3);
|
||
r |= ((csr9.Read32() & 0x08) >> 3) << i; Delay(3);
|
||
csr9.Write32(srom_base_cmd | 0x01); Delay(3);
|
||
}
|
||
|
||
// Get msb
|
||
for (int i = 15; i >= 8; --i) {
|
||
csr9.Write32(srom_base_cmd | 0x03); Delay(3);
|
||
r |= ((csr9.Read32() & 0x08) >> 3) << i; Delay(3);
|
||
csr9.Write32(srom_base_cmd | 0x01); Delay(3);
|
||
}
|
||
|
||
// Finish up
|
||
csr9.Write32(srom_base_cmd); Delay(3);
|
||
|
||
return (ushort)r;
|
||
}
|
||
|
||
private String ConnectionTypeName(uint connectionType)
|
||
{
|
||
switch (connectionType) {
|
||
case 0x0000: return "10BaseT";
|
||
case 0x0100: return "10BaseT Nway";
|
||
case 0x0204: return "10BaseT Full Duplex";
|
||
case 0x0001: return "BNC";
|
||
case 0x0003: return "SYM_SRC (100BaseTx)";
|
||
case 0x0205: return "SYM_SCR";
|
||
case 0x0006: return "100Base-T4";
|
||
case 0x0007: return "100Base-FX";
|
||
case 0x0208: return "100Base-FXFD";
|
||
case 0x0009: return "MII TP";
|
||
case 0x020a: return "MII TP (full-dulex)";
|
||
case 0x000d: return "MII (100Base-Tx)";
|
||
case 0x020e: return "MII (100Base-Tx full duplex)";
|
||
case 0x000f: return "MII (100Base-T4";
|
||
case 0x0010: return "MII (100Base-FX 100Mb/s fiber)";
|
||
case 0x0211:
|
||
return "MII (100Base-FX 100Mb/s fiber full duplex)";
|
||
case 0x0800: return "Power up AutoSense (dynamic)";
|
||
case 0x8800: return "Power up AutoSense";
|
||
case 0xffff: return "No selected media interface";
|
||
default:
|
||
return String.Format("Unknown ({0})", connectionType);
|
||
}
|
||
}
|
||
|
||
private String MediaCodeName(uint mediaCode)
|
||
{
|
||
switch (mediaCode) {
|
||
case 0: return "TP (10MB/s)";
|
||
case 1: return "BNC (10MB/s)";
|
||
case 3: return "SYM_SCR (100Base-Tx)";
|
||
case 4: return "TP full-duplex";
|
||
case 5: return "SYM_SCR full-duplex (100Base-Tx)";
|
||
case 6: return "100Base-T4";
|
||
case 7: return "100Base-FX";
|
||
case 8: return "100Base-FXFD";
|
||
default: return String.Format("Unknown ({1})", mediaCode);
|
||
}
|
||
}
|
||
|
||
private byte[]! GetEthernetAddressBytes(EthernetAddress address)
|
||
{
|
||
byte []! data = (!)address.GetAddressBytes();
|
||
return data;
|
||
}
|
||
|
||
//
|
||
// Setup Frame related methods
|
||
//
|
||
|
||
/// <summary>
|
||
/// Constructs a perfect filtering setup frame buffer.
|
||
/// </summary>
|
||
///
|
||
/// <param name="addresses">The addresses to be present
|
||
/// in the perfect filter up to a maximum of 16.</param>
|
||
private byte[]! MakePerfectFilteringFrame(EthernetAddress[]! addresses)
|
||
requires addresses.Length <= 16;
|
||
{
|
||
//
|
||
// Ref: pages 4.20-4.23
|
||
//
|
||
// Frame has 192 bytes and is laid out thus:
|
||
//
|
||
// <3:0> XX XX a0[1] a0[0] XX = don't care
|
||
// <7:4> XX XX a0[3] a0[2] aN = ethernet address N
|
||
// <11:8> XX XX a0[5] a0[4] aN[i] = i'th byte of address N
|
||
// <15:12> XX XX a1[1] a1[0]
|
||
// <19:16> XX XX a1[3] a1[2]
|
||
// <23:20> XX XX a1[5] a1[4]
|
||
// ...
|
||
// <183:180> XX XX a15[1] a15[0]
|
||
// <187:184> XX XX a15[3] a15[2]
|
||
// <191:188> XX XX a15[5] a15[4]
|
||
//
|
||
// If there are less than 16 addresses to go in the frame,
|
||
// addresses should be repeated to fill all 16 slots.
|
||
//
|
||
// Frame is generated in little endian ordering.
|
||
//
|
||
const int MaxOutIndex = 16;
|
||
int addressIndex = 0;
|
||
int outIndex = 0;
|
||
|
||
byte []! frame = new byte [SetupFrameBytes]; // 192 bytes
|
||
|
||
while (outIndex != MaxOutIndex) {
|
||
int start = outIndex * 6 * 2;
|
||
byte []! address = GetEthernetAddressBytes(
|
||
addresses[addressIndex]);
|
||
frame[start + 0] = address[0];
|
||
frame[start + 1] = address[1];
|
||
frame[start + 4] = address[2];
|
||
frame[start + 5] = address[3];
|
||
frame[start + 8] = address[4];
|
||
frame[start + 9] = address[5];
|
||
addressIndex = (addressIndex + 1) % addresses.Length;
|
||
outIndex ++;
|
||
}
|
||
return frame;
|
||
}
|
||
|
||
private bool WriteStandardSetupFrame()
|
||
{
|
||
txRing.WriteSetupFrame(
|
||
MakePerfectFilteringFrame(
|
||
new EthernetAddress [] { macAddress,
|
||
EthernetAddress.Broadcast }
|
||
),
|
||
FilteringType.Perfect
|
||
);
|
||
TransmitPollDemand();
|
||
|
||
for (int i = 0; i < 100; i++) {
|
||
if (txRing.PollSetupFrameCompleted()) {
|
||
return true;
|
||
}
|
||
Thread.Sleep(TimeSpan.FromMilliseconds(5));
|
||
}
|
||
DebugStub.Break();
|
||
return false;
|
||
}
|
||
}
|
||
}
|