483 lines
18 KiB
C
483 lines
18 KiB
C
//////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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// kd1394.h - 1394 Kernel Debugger DLL
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//
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// Various OHCI definitions
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//
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#define PHY_INITIATE_BUS_RESET 0x40 // IBR @ Address 1
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///////////////////////////////////////////////////////// Register Structures.
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//
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union VERSION_REGISTER {
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struct {
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ULONG Revision:8; // bits 0-7
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ULONG Reserved:8; // bits 8-15
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ULONG Version:8; // bits 16-23
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ULONG GUID_ROM:1; // bit 24
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ULONG Reserved1:7; // bits 25-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(VERSION_REGISTER) == 4);
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union VENDOR_ID_REGISTER {
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struct {
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ULONG VendorCompanyId:24; // bits 0-23
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ULONG VendorUnique:8; // bits 24-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(VENDOR_ID_REGISTER) == 4);
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union GUID_ROM_REGISTER {
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struct {
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ULONG Reserved0:16; // bits 0-15
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ULONG RdData:8; // bits 16-23
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ULONG Reserved1:1; // bit 24
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ULONG RdStart:1; // bit 25
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ULONG Reserved2:5; // bits 26-30
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ULONG AddrReset:1; // bits 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(GUID_ROM_REGISTER) == 4);
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union AT_RETRIES_REGISTER {
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struct {
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ULONG MaxATReqRetries:4; // bits 0-3
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ULONG MaxATRespRetries:4; // bits 4-7
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ULONG MaxPhysRespRetries:4; // bits 8-11
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ULONG Reserved:4; // bits 12-15
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ULONG CycleLimit:13; // bits 16-28
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ULONG SecondLimit:3; // bits 29-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(AT_RETRIES_REGISTER) == 4);
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union CSR_CONTROL_REGISTER {
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struct {
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ULONG CsrSel:2; // bits 0-1
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ULONG Reserved:29; // bits 2-30
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ULONG CsrDone:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(CSR_CONTROL_REGISTER) == 4);
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union CONFIG_ROM_HEADER_REGISTER {
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struct {
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ULONG Rom_crc_value:16; // bits 0-15
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ULONG Crc_length:8; // bits 16-23
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ULONG Info_length:8; // bits 24-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(CONFIG_ROM_HEADER_REGISTER) == 4);
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union BUS_OPTIONS_REGISTER {
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struct {
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ULONG Link_spd:3; // bits 0-2
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ULONG Reserved0:3; // bits 3-5
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ULONG g:2; // bits 6-7
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ULONG Reserved1:4; // bits 8-11
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ULONG Max_rec:4; // bits 12-15
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ULONG Cyc_clk_acc:8; // bits 16-23
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ULONG Reserved2:3; // bits 24-26
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ULONG Pmc:1; // bit 27
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ULONG Bmc:1; // bit 28
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ULONG Isc:1; // bit 29
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ULONG Cmc:1; // bit 30
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ULONG Irmc:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(BUS_OPTIONS_REGISTER) == 4);
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union HC_CONTROL_REGISTER {
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struct {
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ULONG Reserved:16; // bits 0-15
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ULONG SoftReset:1; // bit 16
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ULONG LinkEnable:1; // bit 17
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ULONG PostedWriteEnable:1; // bit 18
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ULONG Lps:1; // bit 19
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ULONG Reserved2:2; // bits 20-21
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ULONG APhyEnhanceEnable:1; // bit 22
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ULONG ProgramPhyEnable:1; // bit 23
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ULONG Reserved3:6; // bits 24-29
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ULONG NoByteSwapData:1; // bit 30
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ULONG Reserved4:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(HC_CONTROL_REGISTER) == 4);
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union FAIRNESS_CONTROL_REGISTER {
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struct {
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ULONG Pri_req:8; // bits 0-7
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ULONG Reserved0:24; // bits 8-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(FAIRNESS_CONTROL_REGISTER) == 4);
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union LINK_CONTROL_REGISTER {
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struct {
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ULONG Reserved0:4; // bits 0-3
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ULONG CycleSyncLReqEnable:1; // bit 4
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ULONG Reserved1:4; // bits 5-8
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ULONG RcvSelfId:1; // bit 9
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ULONG RcvPhyPkt:1; // bit 10
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ULONG Reserved2:9; // bits 11-19
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ULONG CycleTimerEnable:1; // bit 20
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ULONG CycleMaster:1; // bit 21
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ULONG CycleSource:1; // bit 22
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ULONG Reserved3:9; // bits 23-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(LINK_CONTROL_REGISTER) == 4);
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union NODE_ID_REGISTER {
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struct {
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ULONG NodeId:6; // bits 0-5
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ULONG BusId:10; // bits 6-15
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ULONG Reserved1:11; // bits 16-26
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ULONG Cps:1; // bit 27
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ULONG Reserved2:2; // bits 28-29
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ULONG Root:1; // bit 30
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ULONG IdValid:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(NODE_ID_REGISTER) == 4);
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union SELF_ID_BUFFER_REGISTER {
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ULONG SelfIdBufferPointer;
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struct {
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ULONG Reserved0:11; // bits 0-10
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ULONG SelfIdBuffer:21; // bits 11-32
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(SELF_ID_BUFFER_REGISTER) == 4);
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union SELF_ID_COUNT_REGISTER {
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struct {
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ULONG Reserved0:2; // bits 0-1
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ULONG SelfIdSize:11; // bits 2-12
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ULONG Reserved1:3; // bits 13-15
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ULONG SelfIdGeneration:8; // bits 16-23
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ULONG Reserved2:7; // bits 24-30
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ULONG SelfIdError:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(SELF_ID_COUNT_REGISTER) == 4);
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union PHY_CONTROL_REGISTER {
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struct {
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ULONG WrData:8; // bits 0-7
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ULONG RegAddr:4; // bits 8-11
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ULONG Reserved0:2; // bits 12-13
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ULONG WrReg:1; // bit 14
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ULONG RdReg:1; // bit 15
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ULONG RdData:8; // bits 16-23
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ULONG RdAddr:4; // bits 24-27
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ULONG Reserved1:3; // bits 28-30
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ULONG RdDone:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(PHY_CONTROL_REGISTER) == 4);
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union ISOCH_CYCLE_TIMER_REGISTER {
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struct {
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ULONG CycleOffset:12; // bits 0-11
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ULONG CycleCount:13; // bits 12-24
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ULONG CycleSeconds:7; // bits 25-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(ISOCH_CYCLE_TIMER_REGISTER) == 4);
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union INT_EVENT_MASK_REGISTER {
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struct {
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ULONG ReqTxComplete:1; // bit 0
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ULONG RspTxComplete:1; // bit 1
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ULONG ARRQ:1; // bit 2
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ULONG ARRS:1; // bit 3
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ULONG RQPkt:1; // bit 4
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ULONG RSPPkt:1; // bit 5
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ULONG IsochTx:1; // bit 6
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ULONG IsochRx:1; // bit 7
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ULONG PostedWriteErr:1; // bit 8
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ULONG LockRespErr:1; // bit 9
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ULONG Reserved0:6; // bits 10-15
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ULONG SelfIdComplete:1; // bit 16
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ULONG BusReset:1; // bit 17
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ULONG Reserved1:1; // bit 18
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ULONG Phy:1; // bit 19
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ULONG CycleSynch:1; // bit 20
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ULONG Cycle64Secs:1; // bit 21
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ULONG CycleLost:1; // bit 22
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ULONG CycleInconsistent:1; // bit 23
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ULONG UnrecoverableError:1; // bit 24
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ULONG CycleTooLong:1; // bit 25
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ULONG PhyRegRcvd:1; // bit 26
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ULONG Reserved2:3; // bits 27-29
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ULONG VendorSpecific:1; // bit 30
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ULONG MasterIntEnable:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(INT_EVENT_MASK_REGISTER) == 4);
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union COMMAND_POINTER_REGISTER {
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struct {
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ULONG Z:4; // bits 0-3
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ULONG DescriptorAddr:28; // bits 4-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(COMMAND_POINTER_REGISTER) == 4);
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union CONTEXT_CONTROL_REGISTER {
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struct {
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ULONG EventCode:5; // bits 0-4
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ULONG Spd:3; // bits 5-7
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ULONG Reserved0:2; // bits 8-9
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ULONG Active:1; // bit 10
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ULONG Dead:1; // bit 11
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ULONG Wake:1; // bit 12
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ULONG Reserved1:2; // bits 13-14
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ULONG Run:1; // bit 15
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ULONG Reserved2:16; // bits 16-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(CONTEXT_CONTROL_REGISTER) == 4);
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union IT_CONTEXT_CONTROL_REGISTER {
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struct {
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ULONG EventCode:5; // bits 0-4
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ULONG Spd:3; // bits 5-7
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ULONG Reserved0:2; // bits 8-9
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ULONG Active:1; // bit 10
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ULONG Dead:1; // bit 11
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ULONG Wake:1; // bit 12
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ULONG Reserved1:2; // bits 13-14
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ULONG Run:1; // bit 15
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ULONG CycleMatch:15; // bits 16-30
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ULONG CycleMatchEnable:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(IT_CONTEXT_CONTROL_REGISTER) == 4);
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union IR_CONTEXT_CONTROL_REGISTER {
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struct {
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ULONG EventCode:5; // bits 0-4
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ULONG Spd:3; // bits 5-7
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ULONG Reserved0:2; // bits 8-9
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ULONG Active:1; // bit 10
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ULONG Dead:1; // bit 11
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ULONG Wake:1; // bit 12
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ULONG Reserved1:2; // bits 13-14
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ULONG Run:1; // bit 15
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ULONG CycleMatch:12; // bits 16-27
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ULONG MultiChanMode:1; // bit 28
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ULONG CycleMatchEnable:1; // bit 29
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ULONG IsochHeader:1; // bit 30
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ULONG BufferFill:1; // bit 31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(IR_CONTEXT_CONTROL_REGISTER) == 4);
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union CONTEXT_MATCH_REGISTER {
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struct {
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ULONG ChannelNumber:6; // bits 0-5
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ULONG Reserved:1; // bit 6
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ULONG Tag1SyncFilter:1; // bit 7
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ULONG Sync:4; // bits 8-11
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ULONG CycleMatch:13; // bits 12-24
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ULONG Reserved1:3; // bits 25-27
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ULONG Tag:4; // bit 28-31
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(CONTEXT_MATCH_REGISTER) == 4);
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/////////////////////////////////////////////////////////////// Register Sets.
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//
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struct DMA_CONTEXT_REGISTERS {
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CONTEXT_CONTROL_REGISTER ContextControlSet;
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CONTEXT_CONTROL_REGISTER ContextControlClear;
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ULONG Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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ULONG Reserved1[4];
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};
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struct DMA_ISOCH_RCV_CONTEXT_REGISTERS {
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IR_CONTEXT_CONTROL_REGISTER ContextControlSet;
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IR_CONTEXT_CONTROL_REGISTER ContextControlClear;
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ULONG Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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CONTEXT_MATCH_REGISTER ContextMatch;
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ULONG Reserved1[3];
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};
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struct DMA_ISOCH_XMIT_CONTEXT_REGISTERS {
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IT_CONTEXT_CONTROL_REGISTER ContextControlSet;
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IT_CONTEXT_CONTROL_REGISTER ContextControlClear;
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ULONG Reserved0[1];
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COMMAND_POINTER_REGISTER CommandPtr;
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};
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struct OHCI_REGISTER_MAP {
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VERSION_REGISTER Version; // @ 0
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GUID_ROM_REGISTER GUID_ROM; // @ 4
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AT_RETRIES_REGISTER ATRetries; // @ 8
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ULONG CsrData; // @ C
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ULONG CsrCompare; // @ 10
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CSR_CONTROL_REGISTER CsrControl; // @ 14
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CONFIG_ROM_HEADER_REGISTER ConfigRomHeader; // @ 18
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ULONG BusId; // @ 1C
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BUS_OPTIONS_REGISTER BusOptions; // @ 20
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ULONG GuidHi; // @ 24
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ULONG GuidLo; // @ 28
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ULONG Reserved0[2]; // @ 2C
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ULONG ConfigRomMap; // @ 34
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ULONG PostedWriteAddressLo; // @ 38
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ULONG PostedWriteAddressHi; // @ 3C
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VENDOR_ID_REGISTER VendorId; // @ 40
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ULONG Reserved1[3]; // @ 44
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HC_CONTROL_REGISTER HCControlSet; // @ 50
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HC_CONTROL_REGISTER HCControlClear; // @ 54
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ULONG Reserved2[3]; // @ 58
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SELF_ID_BUFFER_REGISTER SelfIdBufferPtr; // @ 64
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SELF_ID_COUNT_REGISTER SelfIdCount; // @ 68
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ULONG Reserved3[1]; // @ 6C
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ULONG IRChannelMaskHiSet; // @ 70
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ULONG IRChannelMaskHiClear; // @ 74
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ULONG IRChannelMaskLoSet; // @ 78
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ULONG IRChannelMaskLoClear; // @ 7C
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INT_EVENT_MASK_REGISTER IntEventSet; // @ 80
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INT_EVENT_MASK_REGISTER IntEventClear; // @ 84
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INT_EVENT_MASK_REGISTER IntMaskSet; // @ 88
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INT_EVENT_MASK_REGISTER IntMaskClear; // @ 8C
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ULONG IsoXmitIntEventSet; // @ 90
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ULONG IsoXmitIntEventClear; // @ 94
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ULONG IsoXmitIntMaskSet; // @ 98
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ULONG IsoXmitIntMaskClear; // @ 9C
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ULONG IsoRecvIntEventSet; // @ A0
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ULONG IsoRecvIntEventClear; // @ A4
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ULONG IsoRecvIntMaskSet; // @ A8
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ULONG IsoRecvIntMaskClear; // @ AC
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ULONG Reserved4[11]; // @ B0
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FAIRNESS_CONTROL_REGISTER FairnessControl; // @ DC
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LINK_CONTROL_REGISTER LinkControlSet; // @ E0
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LINK_CONTROL_REGISTER LinkControlClear; // @ E4
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NODE_ID_REGISTER NodeId; // @ E8
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PHY_CONTROL_REGISTER PhyControl; // @ EC
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ISOCH_CYCLE_TIMER_REGISTER IsochCycleTimer; // @ F0
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ULONG Reserved5[3]; // @ F4
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ULONG AsynchReqFilterHiSet; // @ 100
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ULONG AsynchReqFilterHiClear; // @ 104
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ULONG AsynchReqFilterLoSet; // @ 108
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ULONG AsynchReqFilterLoClear; // @ 10C
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ULONG PhyReqFilterHiSet; // @ 110
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ULONG PhyReqFilterHiClear; // @ 114
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ULONG PhyReqFilterLoSet; // @ 118
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ULONG PhyReqFilterLoClear; // @ 11C
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ULONG PhysicalUpperBound; // @ 120
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ULONG Reserved6[23]; // @ 124
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DMA_CONTEXT_REGISTERS AsynchContext[4]; // @ 180
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// ATRsp_Context; // @ 1A0
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// ARReq_Context; // @ 1C0
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// ARRsp_Context; // @ 1E0
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DMA_ISOCH_XMIT_CONTEXT_REGISTERS IT_Context[32]; // @ 200
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DMA_ISOCH_RCV_CONTEXT_REGISTERS IR_Context[32]; // @ 400
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};
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STATIC_ASSERT(sizeof(OHCI_REGISTER_MAP) == 2048);
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//
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// IEEE 1212 Configuration Rom header definition
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//
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union CONFIG_ROM_INFO {
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struct {
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union {
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USHORT CRI_CRC_Value:16;
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struct {
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UCHAR CRI_Saved_Info_Length;
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UCHAR CRI_Saved_CRC_Length;
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} Saved;
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};
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UCHAR CRI_CRC_Length;
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UCHAR CRI_Info_Length;
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(CONFIG_ROM_INFO) == 4);
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//
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// IEEE 1212 Immediate entry definition
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//
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union IMMEDIATE_ENTRY {
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struct {
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ULONG IE_Value:24;
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ULONG IE_Key:8;
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(IMMEDIATE_ENTRY) == 4);
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//
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// IEEE 1212 Directory definition
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//
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union DIRECTORY_INFO {
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struct {
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union {
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USHORT DI_CRC;
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USHORT DI_Saved_Length;
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};
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USHORT DI_Length;
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};
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ULONG all;
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};
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STATIC_ASSERT(sizeof(DIRECTORY_INFO) == 4);
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//
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///////////////////////////////////////////////////////////////// End of File.
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