217 lines
7.2 KiB
C
217 lines
7.2 KiB
C
//////////////////////////////////////////////////////////////////////////////
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//
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// PCI Structures and declarations.
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//
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// Copyright (c) Microsoft Corporation. All rights reserved.
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//
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//////////////////////////////////////////////////////////////////////////////
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//
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//
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// A PCI driver can read the complete 256 bytes of configuration
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// information for any PCI device.
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// A return value of 0 means that the specified PCI bus does not exist.
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// A return value of 2, with a VendorID of PCI_INVALID_VENDORID means
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// that the PCI bus does exist, but there is no device at the specified
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// VirtualSlotNumber (PCI Device/Function number).
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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struct PCI_COMMON_CONFIG {
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UINT16 VendorID; // (ro)
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UINT16 DeviceID; // (ro)
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UINT16 Command; // Device control
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UINT16 Status;
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UINT8 RevisionID; // (ro)
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UINT8 ProgIf; // (ro)
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UINT8 SubClass; // (ro)
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UINT8 BaseClass; // (ro)
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UINT8 CacheLineSize; // (ro+)
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UINT8 LatencyTimer; // (ro+)
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UINT8 HeaderType; // (ro)
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UINT8 BIST; // Built in self test
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// 0x10:
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union {
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// Devices: (HeaderType & ~PCI_MULTIFUNCTION) == PCI_DEVICE_TYPE
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struct _PCI_HEADER_TYPE_0 {
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// 0x10:
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UINT32 BaseAddresses[PCI_TYPE0_ADDRESSES];
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// 0x28:
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UINT32 Reserved1; // => UINT32 CardBusCisPtr;
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// 0x2C:
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UINT16 SubVendorID;
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// 0x2E:
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UINT16 SubSystemID;
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// 0x30:
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UINT32 ROMBaseAddress;
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// 0x34:
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UINT32 Reserved2[2];
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// 0x3c:
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UINT8 InterruptLine; //
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UINT8 InterruptPin; // (ro)
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UINT8 MinimumGrant; // (ro)
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UINT8 MaximumLatency; // (ro)
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// 0x40:
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} type0;
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// Bridges: (HeaderType & ~PCI_MULTIFUNCTION) == PCI_BRIDGE_TYPE
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struct _PCI_HEADER_TYPE_1 {
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// 0x10:
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UINT32 BaseAddresses[PCI_TYPE1_ADDRESSES];
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// 0x18:
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UINT8 PrimaryBus;
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UINT8 SecondaryBus;
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UINT8 SubordinateBus;
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UINT8 SecondaryLatency;
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// 0x1c:
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UINT8 IOBase;
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UINT8 IOLimit;
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UINT16 SecondaryStatus;
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// 0x20:
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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// 0x24:
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UINT16 PrefetchBase;
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UINT16 PrefetchLimit;
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// 0x28:
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UINT32 PrefetchBaseUpper32;
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// 0x2c:
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UINT32 PrefetchLimitUpper32;
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// 0x30:
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UINT16 IOBaseUpper16;
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UINT16 IOLimitUpper16;
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// 0x34:
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UINT32 Reserved;
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// 0x38:
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UINT32 ROMBaseAddress;
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// 0x3c:
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UINT8 InterruptLine;
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UINT8 InterruptPin;
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UINT16 BridgeControl;
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// 0x40:
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} type1;
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};
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// 0x40:
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UINT8 DeviceSpecific[192];
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};
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#define PCI_FIXED_HDR_LENGTH 16 // Through BIST
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#define PCI_COMMON_HDR_LENGTH 64 // Through union
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#define PCI_MAX_BUSES 128
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_INVALID_VENDORID 0xFFFF
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//
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// Bit encodings for PCI_COMMON_CONFIG.HeaderType
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//
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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//
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// Bit encodings for PCI_COMMON_CONFIG.Command
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//
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040 // (ro+)
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#define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+)
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#define PCI_ENABLE_SERR 0x0100 // (ro+)
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro)
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//
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// Bit encodings for PCI_COMMON_CONFIG.Status
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//
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro)
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses
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//
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#define PCI_BAR_MEMORY_TYPE_MASK 0x00000006 // (ro)
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#define PCI_BAR_MEMORY_TYPE_32BIT 0x00000000
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#define PCI_BAR_MEMORY_TYPE_64BIT 0x00000004
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#define PCI_BAR_MEMORY_PREFETCHABLE 0x00000008 // (ro)
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#define PCI_BAR_TYPE_MASK 0x00000003
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#define PCI_BAR_TYPE_IO_SPACE 0x00000001 // (ro)
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#define PCI_BAR_TYPE_MEMORY 0x00000000
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#define PCI_BAR_ADDRESS_MASK 0xfffffff0
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses
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//
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#define PCI_ROMADDRESS_ENABLED 0x00000001
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#define PCI_ROMADDRESS_MASK 0xfffff800
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//
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// Reference notes for PCI configuration fields:
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//
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// ro these field are read only. changes to these fields are ignored
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//
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// ro+ these field are intended to be read only and should be initialized
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// by the system to their proper values. However, driver may change
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// these settings.
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//
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// ---
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//
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// All resources consumed by a PCI device start as uninitialized
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// under NT. An uninitialized memory or I/O base address can be
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// determined by checking its corresponding enabled bit in the
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// PCI_COMMON_CONFIG.Command value. An InterruptLine is uninitialized
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// if it contains the value of -1.
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//
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type1.BridgeControl
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//
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#define PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001
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#define PCI_ENABLE_BRIDGE_SERR 0x0002
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#define PCI_ENABLE_BRIDGE_ISA 0x0004
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#define PCI_ENABLE_BRIDGE_VGA 0x0008
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#define PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020
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#define PCI_ASSERT_BRIDGE_RESET 0x0040
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#define PCI_ENABLE_BRIDGE_FAST_BACK_TO_BACK 0x0080
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//
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// Definitions needed for Access to Hardware Type 1
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//
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#define PCI_ADDR_PORT 0xcf8
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#define PCI_DATA_PORT 0xcfc
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union PCI_CONFIG_BITS {
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struct {
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UINT32 offset : 8;
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UINT32 function : 3;
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UINT32 device : 5;
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UINT32 bus : 15;
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UINT32 enable : 1;
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} bits;
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UINT32 value;
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};
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///////////////////////////////////////////////////////////////// End of File.
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