12 lines
435 B
Markdown
12 lines
435 B
Markdown
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# riscv
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This is the RISC-V emulation core that LCPU uses in its native emulation module.
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This is based off [cnlohr/mini-rv32ima](https://github.com/cnlohr/mini-rv32ima), but:
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- Rewritten in C++20 (because I like sanity)
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- Cleaned up somewhat
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- Moved *ALL* device and MMIO code to seperate interfaces
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- Re-implemented the timer device and the UART as said oop interface
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- Lua devices use a wrapper which can contain lua callbacks
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