gmod-lcpu/native/projects/riscv
Lily Tsuru 90e684e1e3 riscv: implement syscon + system hooks
This finally allows the test harness to cleanly shut down. Awesome!

This commit also reformats the whole project's native code. Oops!
2023-07-24 01:56:50 -04:00
..
include/riscv riscv: implement syscon + system hooks 2023-07-24 01:56:50 -04:00
src riscv: implement syscon + system hooks 2023-07-24 01:56:50 -04:00
CMakeLists.txt wow holy shit lily finally figured out how to work on the cpu core! 2023-07-23 05:19:08 -04:00
README.md riscv: IT WORKS 2023-07-24 00:01:39 -04:00

README.md

riscv

This is a simple RISC-V RV32IMA emulation library.

This is based off cnlohr/mini-rv32ima, but:

  • Rewritten in C++20 (because I like sanity)
  • Cleaned up vastly
  • Moved ALL device and MMIO code to seperate interfaces

Depends on lucore.

Usage

TBD (if this is moved to another repo). See the riscv_test_harness project.