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gmod-lcpu/native/projects/riscv
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Lily Tsuru abe9b78b1a oops 2023-07-23 05:24:26 -04:00
..
include/riscv oops 2023-07-23 05:24:26 -04:00
src wow holy shit lily finally figured out how to work on the cpu core! 2023-07-23 05:19:08 -04:00
CMakeLists.txt wow holy shit lily finally figured out how to work on the cpu core! 2023-07-23 05:19:08 -04:00
README.md riscv: Implement partial CLINT and SYSCON. 2023-07-22 22:43:49 -04:00

README.md

riscv

This is a simple RISC-V RV32IMA emulation library.

This is based off cnlohr/mini-rv32ima, but:

  • Rewritten in C++20 (because I like sanity)
  • Cleaned up vastly
  • Moved ALL device and MMIO code to seperate interfaces

Depends on lucore.