369 lines
14 KiB
NASM
369 lines
14 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; Microsoft Research Singularity
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;;;
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;;; Copyright (c) Microsoft Corporation. All rights reserved.
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;;;
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;;; This file contains ARM-specific assembly code.
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;;;
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; Copyright (C) Advanced RISC Machines Limited, 1994. All rights reserved.
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;
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; RCS Revision: 1
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; Checkin Date: 2007/06/29 02:59:16
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; Revising Author
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GET fpe.asm
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GET kxarm.inc
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CodeArea |.text|
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IMPORT FPE_Raise
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SNaNInf EQU NaNInfExp_Single - EIExp_bias + SExp_bias
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DNaNInf EQU NaNInfExp_Double - EIExp_bias + DExp_bias
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DExp_max EQU 2047
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SFrac_len EQU 23
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exp RN 3
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sign RN 2
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tmp RN 12
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;==============================================================================
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;Format conversions
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[ :DEF: d2f_s
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; Local storage size and offsets
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LOC_SIZE EQU 0x18
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OrgOp1h EQU 0x14
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OrgOp1l EQU 0x10
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ExDResl EQU 0x08
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NewResl EQU 0x10
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; Ensure the defines are what they should be. Note that there was
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; a problem when we swapped the double halves as the code relied on
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; the low half of the double not being the register where floats are
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; returned. I have put these asserts here so the registers don't
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; change out from under me. We don't really need these conditions
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; to hold true, just the code needs to be checked after register
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; defines are changed.
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ASSERT exp = r3
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ASSERT sign = r2
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ASSERT tmp = r12
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ASSERT dOPh = r1
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ASSERT dOPl = r0
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ASSERT fOP = r0
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Export __dtos
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NESTED_ENTRY __dtos
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EnterWithLR_16
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STMFD sp!, {r4, lr} ; Save off non-volatile, lr
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SUB sp, sp, #LOC_SIZE ; Allocate stack space
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PROLOG_END
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STR r1, [sp, #OrgOp1h] ; Save off arg in case of exception
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MOV r4, #_FpDToS ; Set double->float convert
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ORRS tmp, dOPl, dOPh, LSL #1 ; Special check for zero
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STR r0, [sp, #OrgOp1l] ; Save off arg in case of exception
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BEQ __dtos_return_zero ; If zero, return it
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AND sign, dOPh, #Sign_bit
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MOV tmp, #(DExp_bias - SExp_bias) << (DExp_pos+1)
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RSB dOPh, tmp, dOPh, LSL #1
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MOVS exp, dOPh, LSR #DExp_pos+1
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BEQ _d2f_ExpUnderflow
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CMP exp, #254
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BHS _d2f_uncommon
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_d2f_round
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MOVS tmp, dOPl, LSL #3 ; Check for inexact
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ORRNE r4, r4, #INX_bit ; Raise inexact if inexact
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ORRS tmp, sign, dOPl, LSR #29
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MOV r3, dOPl ; * Need to save dOPl somewhere else
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ADC fOP, tmp, dOPh, LSL #2 ; dOPh already shifted 1 bit
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BCC __dtos_return
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MOVS r3, r3, LSL #4 ; * Was: MOVS dOPl, dOPl, LSL #4
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BNE __dtos_return
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BIC fOP, fOP, #1
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B __dtos_return
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_d2f_uncommon ; exp out of range - check for special cases
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CMP exp, #(-(DExp_bias - SExp_bias)) :AND: 0x7FF
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BHS _d2f_ExpUnderflow
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; if exponent 254 - test for overflow during rounding
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CMP exp, #254
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MOVEQ tmp, dOPh, LSL #DExp_len
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ORREQ tmp, tmp, dOPl, LSR #DFhi_len
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CMNEQ tmp, #1 << 8 ; check if dOP rounds to overflow
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BLO _d2f_round ; no - continue (8 clk overhead)
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_d2f_ExpOverflow ; overflow, inf/NaN
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ADD exp, exp, #1
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TEQ exp, #DExp_max - DExp_bias + SExp_bias + 1
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MOVNE fOP, sign
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BNE __dtos_return_overflow ; overflow
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_d2f_Inf_or_NaN ; found inf or NaN
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ORRS tmp, dOPl, dOPh, LSL #DExp_len ; infinity if EQ
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MOVEQ tmp, #0xFF000000
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ORR fOP, sign, tmp, LSR #1 ; return signed infinity
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BEQ __dtos_return
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; sign in fOP
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MOVS tmp, dOPh, LSL #DExp_len
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ORRPL r4, r4, #IVO_bit ; Set invalid if SNaN
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LDR r2, fNaN ; Return quiet NaN
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MOV tmp, dOPh, LSL #DExp_len-9 ; insert high mantissa bits
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ORR tmp, tmp, dOPl, LSR #29 ; insert low mantissa bits
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ORR r0, r2, tmp ; Set exp, high mant bit
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B __dtos_return
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fNaN DCD &7FC00000
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__dtos_return_zero
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MOV fOP, dOPh ; dOPh has the correctly signed
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B __dtos_return ; float zero, so return it
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_d2f_ExpUnderflow
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CMP exp, #0
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SUBNE exp, exp, #0x800
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; was underflow - return denorm or zero (exp is -X .. 0)
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RSB exp, exp, #SExp_len+1 ; right shift for dOPh
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RSBS tmp, exp, #33 ; left shift for dOPh rounding bits
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MOVLS fOP, sign ; LO: shift larger than 33 -> return signed zero
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ORRLS r4, r4, #UNF_bit :OR: INX_bit
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BLS __dtos_return
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MOV dOPh, dOPh, LSL #DExp_len-1 ; dOPh shift left 1 bit
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ORR dOPh, dOPh, dOPl, LSR #DFhi_len+1
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ORR dOPh, dOPh, #1 << 31
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MOVS tmp, dOPh, LSL tmp ; CS -> round
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ORRNE r4, r4, #UNF_bit :OR: INX_bit
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MOV tmp, dOPl ; save dOPl since we may need it
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ADC fOP, sign, dOPh, LSR exp
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BCC __dtos_return
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MOVEQS tmp, tmp, LSL #32 - (DFhi_len+1) ; * Was: MOVEQS dOPl, dOPl, LSL #32
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BICEQ fOP, fOP, #1
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B __dtos_return
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__dtos_return_overflow
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ORR r4, r4, #OVF_bit :OR: INX_bit ; Set exception information
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AND r0, r0, #0x80000000 ; Keep sign bit
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MOV r1, #0xFF000000 ; Set exponent to max
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ORR r0, r0, r1, LSR #1 ; ..
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__dtos_return
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TST r4, #FPECause_mask ; Check for exceptions
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MOV r1, r4 ; Move exception info.
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ADDEQ sp, sp, #LOC_SIZE ; If none, pop input arg
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {r4, lr} ; restore r4 and return
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BXEQ lr
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ELSE
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LDMEQFD sp!, {r4, pc} ; restore r4 and return
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ENDIF
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STR r0, [sp, #ExDResl] ; Store default result
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LDR r2, [sp, #OrgOp1l] ; Load original arg
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LDR r3, [sp, #OrgOp1h] ; ..
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ADD r0, sp, #NewResl ; Pointer to new result
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CALL FPE_Raise ; Deal with exception info.
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IF Thumbing :LAND: :LNOT: Interworking
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CODE16
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bx pc ; switch back to ARM mode
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nop
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CODE32
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ENDIF
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LDR r0, [sp, #NewResl] ; Load new result
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ADD sp, sp, #LOC_SIZE ; Pop exception record, arg
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {r4, lr} ; Restore r4 and return
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BX lr
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ELSE
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LDMFD sp!, {r4, pc} ; Restore r4 and return
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ENDIF
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ENTRY_END __dtos
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]
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;------------------------------------------------------------------------------
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[ :DEF: f2d_s
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LOC_SIZE EQU 0x18
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OrgOp1l EQU 0x14
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ExDResh EQU 0x0c
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ExDResl EQU 0x08
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NewResh EQU 0x14
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NewResl EQU 0x10
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Export __stod
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IMPORT FPE_Raise
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; Ensure the defines are what they should be. Note that there was
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; a problem when we swapped the double halves as the code relied on
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; the low half of the double not being the register where floats are
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; passed. I have put these asserts here so the registers don't
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; change out from under me. We don't really need these conditions
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; to hold true, just the code needs to be checked after register
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; defines are changed.
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ASSERT exp = r3
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ASSERT sign = r2
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ASSERT tmp = r12
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ASSERT dOPh = r1
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ASSERT dOPl = r0
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ASSERT fOP = r0
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NESTED_ENTRY __stod
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EnterWithLR_16
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STMFD sp!, {lr} ; Save return address
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SUB sp, sp, #LOC_SIZE ; Allocate local storage
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PROLOG_END
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STR r0, [sp, #OrgOp1l] ; Store original arg in case of exception
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ADD tmp, fOP, #1 << SExp_pos ; filter out inf/NaN/denorm/zero
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TST tmp, #254 << SFrac_len
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BEQ _f2d_uncommon
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MOV tmp, fOP
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MOV dOPl, tmp, LSL #32 - 3
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MOVS dOPh, tmp, ASR #3
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ADD dOPh, dOPh, #(DExp_bias - SExp_bias) << DExp_pos
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ADDPL sp, sp, #LOC_SIZE
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IF Interworking :LOR: Thumbing
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LDMPLFD sp!, {lr}
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BXPL lr
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ELSE
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LDMPLFD sp!, {pc}
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ENDIF
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SUB dOPh, dOPh, #0x700 << DExp_pos
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ADD sp, sp, #LOC_SIZE
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr}
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BX lr
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ELSE
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LDMFD sp!, {pc}
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ENDIF
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_f2d_uncommon
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TST tmp, #1 << SExp_pos ; inf/NaN -> EQ, zero/denorm ->NE
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MOV tmp, fOP
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BEQ _f2d_Inf_or_NaN
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_f2d_denorm
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MOVS dOPl, tmp, LSL #1 ; zero -> EQ
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MOVEQ dOPh, tmp
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ADDEQ sp, sp, #LOC_SIZE ; dOPl zero, dOPh sign bit
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr}
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc}
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ENDIF
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; We have a denormal that must be normalized. The exponent and sign
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; are initialized, then the input argument's mantissa is shifted left
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; until the hidden one is left justified. The exponent is adjusted to
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; account for the shifts. Then the hidden one is removed and the
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; final result assembled.
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AND exp, tmp, #Sign_bit ; Extract sign
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ADD r1, exp, #(DExp_bias-SExp_bias) << DExp_pos
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; Initialize exponent
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MOV r0, tmp, LSL #9 ; Extract mantissa and left justify
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MOVS r2, r0, LSR #16 ; Any high 16 bits set?
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SUBEQ r1, r1, #16 << DExp_pos ; If not, adjust exponent
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MOVEQ r0, r0, LSL #16 ; shift mantissa
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TST r0, #0xFF000000 ; Any high 8 bits set?
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SUBEQ r1, r1, #8 << DExp_pos ; If not, adjust exponent
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MOVEQ r0, r0, LSL #8 ; shift mantissa
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TST r0, #0xF0000000 ; Any high 4 bits set?
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SUBEQ r1, r1, #4 << DExp_pos ; If not, adjust exponent
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MOVEQ r0, r0, LSL #4 ; shift mantissa
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TST r0, #0xC0000000 ; Any high 2 bits set?
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SUBEQ r1, r1, #2 << DExp_pos ; If not, adjust exponent
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MOVEQS r0, r0, LSL #2 ; shift mantissa
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MOVPL r0, r0, LSL #1 ; If high bit clear, adjust exponent
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SUBPL r1, r1, #1 << DExp_pos ; shift mantissa
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MOV r0, r0, LSL #1 ; Account for hidden 1
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ORR r1, r1, r0, LSR #12 ; Form sign, exp, high mantissa
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MOV r0, r0, LSL #20 ; Form low mantissa
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ADD sp, sp, #LOC_SIZE ; Restore stack and
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr} ; return
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BX lr
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ELSE
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LDMFD sp!, {pc} ; return
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ENDIF
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_f2d_Inf_or_NaN ; fOP is NaN/infinity.
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MOVS dOPl, tmp, LSL #SExp_len+1 ; EQ -> inf
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ORREQ dOPh, tmp, #0x007 << DExp_pos ; tranform float inf to double inf
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ADDEQ sp, sp, #LOC_SIZE ; Restore stack and
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IF Interworking :LOR: Thumbing
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LDMEQFD sp!, {lr} ; return
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BXEQ lr
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ELSE
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LDMEQFD sp!, {pc} ; return
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ENDIF
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; MI if quiet NaN - sign in fOP
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BPL __stod_snan
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; Have a QNaN so copy the mantissa bits and return the QNaN
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MOV dOPh, tmp, ASR #3 ; Load mantissa high, sign
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MOV dOPl, tmp, LSL #29 ; Load mantissa low
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ORR dOPh, dOPh, #0x70000000 ; Force exp to max
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ADD sp, sp, #LOC_SIZE ; Restore stack and
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IF Interworking :LOR: Thumbing
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LDMFD sp!, {lr} ; return
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BX lr
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ELSE
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LDMFD sp!, {pc} ; return
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ENDIF
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__stod_snan ; Got an SNaN so raise exception
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LDR r2, [sp, #OrgOp1l] ; Load original operand
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MOV r1, r12, ASR #3 ; Load mantissa high, sign
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MOV r0, r12, LSL #29 ; Load mantissa low
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ORR r1, r1, #0x70000000 ; Force exp to max
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ORR r1, r1, #0x00080000 ; Make QNaN
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STR r1, [sp, #ExDResh] ; Store default result
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STR r0, [sp, #ExDResl] ; ..
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ADD r0, sp, #NewResl ; Pointer to return result
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MOV r1, #_FpSToD ; Load opcode and exception info.
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ORR r1, r1, #IVO_bit ; ..
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CALL FPE_Raise ; Deal with exception info.
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||
|
|
|
||
|
|
IF Thumbing :LAND: :LNOT: Interworking
|
||
|
|
CODE16
|
||
|
|
bx pc ; switch back to ARM mode
|
||
|
|
nop
|
||
|
|
CODE32
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
LDR r1, [sp, #NewResh] ; Load new return value
|
||
|
|
LDR r0, [sp, #NewResl] ; ..
|
||
|
|
ADD sp, sp, #LOC_SIZE ; Pop space off stack
|
||
|
|
IF Interworking :LOR: Thumbing
|
||
|
|
LDMFD sp!, {lr} ; Return
|
||
|
|
BX lr
|
||
|
|
ELSE
|
||
|
|
LDMFD sp!, {pc} ; Return
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
ENTRY_END __stod
|
||
|
|
]
|
||
|
|
|
||
|
|
;==============================================================================
|
||
|
|
|
||
|
|
END
|